TAS6424L-Q1 Datasheet, PDF (27/65 Pages) Texas Instruments – 27-W, 2-MHz Digital Input 4-Channel Automotive Class-D Audio Amplifier With Load-Dump Protection and I2C Diagnostics

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TAS6424L-Q1
SLOS809 – MARCH 2017
9.5.3 Random Write
As shown in Figure 23, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I²C device address and the R/W bit. The R/W bit determines the direction of the data
transfer. For a write data transfer, the R/W bit is a 0. After receiving the correct I²C device address and the R/W
bit, the device responds with an acknowledge bit. Next, the master transmits the address byte or bytes
corresponding to the internal memory address being accessed. After receiving the address byte, the device
again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the
memory address being accessed. After receiving the data byte, the device again responds with an acknowledge
bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
I²C Device Address
and R/W Bit
Subaddress
Figure 23. Random Write Transfer
Data Byte
Stop
Condition
9.5.4 Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master to the device as shown in Figure 24. After receiving each data byte, the device
responds with an acknowledge bit and the I²C subaddress is automatically incremented by one.
Start
Condition
Acknowledge
Acknowledge Acknowledge
Acknowledge Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4 A3 A1 A0 ACK D7 D0 ACK D7
D0 ACK D7 D0 ACK
I²C Device Address
and R/W Bit
Subaddress
First Data Byte
Other Data Byte
Figure 24. Sequential Write Transfer
Last Data Byte
Stop
Condition
9.5.5 Random Read
As shown in Figure 25, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I²C device address and the R/W bit. For the data-read transfer, both a write followed by
a read occur. Initially, a write occurs to transfer the address byte or bytes of the internal memory address to be
read. As a result, the R/W bit is a 0. After receiving the address and the R/W bit, the device responds with an
acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device
transmits another start condition followed by the address and the R/W bit again. This time the R/W bit is a 1,
indicating a read transfer. After receiving the address and the R/W bit, the device again responds with an
acknowledge bit. Next, the device transmits the data byte from the memory address being read. After receiving
the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the
single-byte data-read transfer.
Start
Condition
Acknowledge
Repeat Start
Condition
Acknowledge
Acknowledge
Not
Acknowledge
A6 A5 A1 A0 R/W ACK A7 A6 A5 A4 A0 ACK
A6 A5 A1 A0 R/W ACK D7 D6 D0 D6 ACK
I²C Device Address
and R/W Bit
Subaddress
I²C Device Address
and R/W Bit
Figure 25. Random Read Transfer
Data Byte
Stop
Condition
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