DAC7678_14 Datasheet, PDF (27/53 Pages) Texas Instruments – 12-Bit, Octal-Channel, Ultra-Low Glitch, Voltage Output, Two-Wire Interface Digital-to-Analog Converter with 2.5V Internal Reference

DAC7678
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and 1-bit acknowledge can continue as long as
necessary.
• To signal the end of the data transfer, the master
generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see
Figure 89). This action releases the bus and stops
the communication link with the addressed slave.
All I²C-compatible devices recognize the stop
condition. Upon receipt of a stop condition, the
bus is released, and all slave devices then wait for
a start condition followed by a matching address.
SDA
SCL
Data Line Stable;
Data Valid
Change of Data Allowed
Figure 91. Bit Transfer on the I²C Bus
HS Mode Protocol
• When the bus is idle, both the SDA and SCL lines
are pulled high by the pull-up resistors.
• The master generates a start condition followed
by a valid serial byte containing H/S master code
00001XXX. This transmission is made in F/S
mode at no more than 1.0 Mbps. No device is
allowed to acknowledge the H/S master code, but
SBAS493A – FEBRUARY 2010 – REVISED AUGUST 2010
all devices must recognize it and switch their
internal setting to support 3.4Mbps operation.
• The master then generates a repeated start
condition (a repeated start condition has the same
timing as the start condition). After this repeated
start condition, the protocol is the same as
F/S-mode, except that transmission speeds up to
3.4Mbps are allowed. A stop condition ends HS
mode and switches all the internal settings of the
slave devices to support F/S-mode. Instead of
using a stop condition, repeated start conditions
should be used to secure the bus in H/S-mode.
DAC7678 I²C UPDATE SEQUENCE
For a single update, the DAC7678 requires a start
condition, a valid I²C address, a command and
access (CA) byte, and two data bytes, the most
significant data byte (MSDB) and least significant
data byte (LSDB), as shown in Table 7.
After each byte is received, the DAC7678
acknowledges by pulling the SDA line low during the
high period of a single clock pulse, as shown in
Figure 92. These four bytes and acknowledge cycles
make up the 36 clock cycles required for a single
update to occur. A valid I²C address selects the
DAC7678.
Recognize START or
REPEATED START
Condition
SDA
MSB
Address
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
Recognize STOP or
REPEATED START
Condition
P
Sr
SCL
S
or
Sr
1
2
START or
REPEATED START
Condition
R/W
7
8
9
ACK
1
2
Clock Line Held Low While
Interrupts are Serviced
Figure 92. I²C Bus Protocol
3-8
9
ACK
Sr
or
P
REPEATED START or
STOP
Condition
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