CC2560A Datasheet, PDF (27/52 Pages) Texas Instruments – Dual-Mode Bluetooth Controller

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CC2560A NRND; CC2564 NRND
CC2560A, CC2560B, CC2564, CC2564B
SWRS121E – JULY 2012 – REVISED JANUARY 2016
• Power management using the software messages:
– WAKEUP
– WOKEN
– SLEEP
• CRC data integrity check
For more information on the H5 UART protocol, see Volume 4 Host Controller Interface, Part D Three-
Wire UART Transport Layer of the Bluetooth Core Specifications (www.bluetooth.org/en-
us/specification/adoptedspecifications).
6.4.3 Digital Codec Interface
The codec interface is a fully programmable port to support seamless interfacing with different PCM and
I2S codec devices. The interface includes the following features:
• Two voice channels
• Master and slave modes
• All voice coding schemes defined by the Bluetooth specification: linear, A-Law, and μ-Law
• Long and short frames
• Different data sizes, order, and positions
• High flexibility to support a variety of codecs
• Bus sharing: Data_Out is in Hi-Z state when the interface is not transmitting voice data.
6.4.3.1 Hardware Interface
The interface includes four signals:
• Clock: configurable direction (input or output)
• Frame_Sync and Word_Sync: configurable direction (input or output)
• Data_In: input
• Data_Out: output or 3-state
The CC256x device can be the master of the interface when generating the Clock and Frame_Sync
signals or the slave when receiving these two signals.
For slave mode, clock input frequencies of up to 15 MHz are supported. At clock rates above 12 MHz, the
maximum data burst size is 32 bits.
For master mode, the device can generate any clock frequency between 64 kHz and 4.096 MHz.
6.4.3.2 I2S
When the codec interface is configured to support the I2S protocol, these settings are recommended:
• Bidirectional, full-duplex interface
• Two time slots per frame: time slot-0 for the left channel audio data; and time slot-1 for the right
channel audio data
• Each time slot is configurable up to 40 serial clock cycles long, and the frame is configurable up to 80
serial clock cycles long.
6.4.3.3 Data Format
The data format is fully configurable:
• The data length can be from 8 to 320 bits in 1-bit increments when working with 2 channels, or up to
640 bits when working with 1 channel. The data length can be set independently for each channel.
• The data position within a frame is also configurable within 1 clock (bit) resolution and can be set
independently (relative to the edge of the Frame_Sync signal) for each channel.
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Detailed Description
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