ADC07D1520_12 Datasheet, PDF (27/52 Pages) Texas Instruments – Low Power, 7-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter

ADC07D1520
features is replaced with register-based control and those pin-based controls are disabled. These pins are OutV (pin 3), OutEdge/
DDR (pin 4), FSR (pin 14) and CalDly/DES (pin 127). See 1.2 NON-EXTENDED AND EXTENDED CONTROL MODE for details
on the Extended Control Mode.
1.1.4 The Analog Inputs
The ADC07D1520 must be driven with a differential input signal. Operation with a single-ended signal is not recommended. It is
important that the inputs either be a.c. coupled to the inputs with the V_CMO (pin 7) grounded, or d.c. coupled with the V_CMO pin left
floating. An input common mode voltage equal to the V_CMO output must be provided as the common mode input voltage to V_IN+
and V_IN- when d.c. coupling is used.
Two full-scale range settings are provided via pin 14 (FSR). In Non-extended Control Mode, a logic high on pin 14 causes an input
full-scale range setting of a normal V_IN input level, while a logic low on pin 14 causes an input full-scale range setting of a reduced
V_IN input level. The full-scale range setting operates on both ADCs.
In the Extended Control Mode, programming the Input Full-Scale Voltage Adjust register allows the input full-scale range to be
adjusted as described in 1.4 REGISTER DESCRIPTION and 2.2 THE ANALOG INPUT.
1.1.5 Clocking
The ADC07D1520 must be driven with an a.c. coupled, differential clock signal. 2.3 THE CLOCK INPUTS describes the use of the
clock input pins. A differential LVDS output clock is available for use in latching the ADC output data into whatever device is used
to receive the data.
The ADC07D1520 offers output clocking options: two of these options are Single Data Rate (SDR) and Double Data Rate (DDR).
In SDR mode, the user has a choice of which Data Clock (DCLK) edge, rising or falling, the output data transitions on.
The ADC07D1520 also has the option to use a duty cycle corrected clock receiver as part of the input clock circuit. This feature is
enabled by default and provides improved ADC clocking, especially in the Dual-Edge Sampling (DES) Mode. This circuitry allows
the ADC to be clocked with a signal source having a duty cycle ratio of 20%/80% (worst case) for both the Non-DES and the DES
Modes.
1.1.5.1 Dual-Edge Sampling
The Dual-Edge Sampling (DES) Mode allows either of the ADC07D1520's inputs (I- or Q-channel) to be sampled by both ADCs.
One ADC samples the input on the rising edge of the input clock and the other ADC samples the same input on the falling edge of
the input clock. A single input is thus sampled twice per input clock cycle, resulting in an overall sample rate of twice the input clock
frequency, or 3 GSPS with a 1.5 GHz input clock.
In this mode, the outputs must be carefully interleaved to reconstruct the sampled signal. If the device is programmed into the 1:4
Demux DES Mode, the data is effectively demultiplexed by 1:4. If the input clock is 1.5 GHz, the effective sampling rate is doubled
to 3 GSPS and each of the 4 output buses has an output rate of 750 MHz. All data is available in parallel. To properly reconstruct
the sampled waveform, the four bytes of parallel data that are output with each clock are in the following sampling order, from the
earliest to the latest, and must be interleaved as such: DQd, DId, DQ, DI. Table 1 indicates what the outputs represent for the
various sampling possibilities. If the device is programmed into the Non-demux DES Mode, two bytes of parallel data are output
with each edge of the clock in the following sampling order, from the earliest to the latest: DQ, DI. See Table 2.
In the Non-extended Control and DES Mode of operation, only the I-channel can be sampled. In the Extended Control Mode of
operation, the user can select which input is sampled.
The ADC07D1520 also includes an automatic clock phase background adjustment in DES Mode to automatically and continuously
adjust the clock phase of the I- and Q-channels. This feature removes the need to adjust the clock phase setting manually and
provides optimal DES Mode performance.
TABLE 1. Input Channel Samples Produced at Data Outputs in 1:2 Demultiplexed Mode**
Data Outputs
(Always sourced with
respect to fall of DCLK+)
Non-DES Sampling Mode
Dual-Edge Sampling (DES) Mode
I-Channel Selected
Q-Channel Selected *
DI
I-channel sampled with fall of CLK,
13 cycles earlier.
I-channel sampled with fall Q-channel sampled with fall
of CLK,
of CLK,
13 cycles earlier.
13 cycles earlier.
DId
I-channel sampled with fall of CLK,
14 cycles earlier.
I-channel sampled with fall Q-channel sampled with fall
of CLK,
of CLK,
14 cycles earlier.
14 cycles earlier.
DQ
Q-channel sampled with fall of CLK,
I-channel sampled with rise
of CLK,
Q-channel sampled with rise
of CLK,
13 cycles earlier.
13.5 cycles earlier.
13.5 cycles earlier.
DQd
Q-channel sampled with fall of CLK,
14 cycles earlier.
I-channel sampled with rise
of CLK,
14.5 cycles earlier.
Q-channel sampled with rise
of CLK,
14.5 cycles earlier.
* Note that, in DES Mode and Non-extended Control Mode, only the I-channel is sampled. In DES Mode and Extended Control Mode, the I- or Q-channel can be
sampled.
** Note that, in the Non-demux Mode (DES and Non-DES Mode), the DId and DQd outputs are disabled and are high impedance.
Copyright © 1999-2012, Texas Instruments Incorporated
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