5962-9086302M3A Datasheet, PDF (27/39 Pages) Texas Instruments – VOICE-BAND ANALOG INTERFACE CIRCUITS

TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
serial port — AIC output signals
t_c(SCLK)
t_f(SCLK)
t_r(SCLK)
t_d(CH-FL)
t_d(CH-FH)
t_d(CH-DR)
t_d(CH-EL)
t_d(CH-EH)
t_f(EODX)
t_f(EODR)
t_d(CH-EL)
t_d(CH-EH)
t_d(MH-SL)
t_d(MH-SH)
Shift clock (SCLK) cycle time
Shift clock (SCLK) fall time
Shift clock (SCLK) rise time
Shift clock (SCLK) duty cycle
Delay from SCLK↑ to FSR / FSX ↓
Delay from SCLK↑ to FSR / FSX ↑
DR valid after SCLK↑
Delay from SCLK↑ to EODX / EODR↓ in word mode
Delay from SCLK↑ to EODX / EODR↑ in word mode
EODX fall time
EODR fall time
Delay from SCLK↑ to EODX / EODR↓ in byte mode
Delay from SCLK↑ to EODX / EODR↑ in byte mode
Delay from MSTR CLK↑ to SCLK↓
Delay from MSTR CLK↑ to SCLK↑
serial port — AIC output signals, TLC32044M
t_c(SCLK)
t_f(SCLK)
t_r(SCLK)
Shift clock (SCLK) cycle time
Shift clock (SCLK) fall time
Shift clock (SCLK) rise time
Shift clock (SCLK) duty cycle
t_d(CH-FL)
Delay from SCLK↑ to FSR / FSX ↓
t_d(CH-FH)
Delay from SCLK↑ to FSR / FSX ↑
t_d(CH-DR)
DR valid after SCLK↑
t_d(CH-EL)
Delay from SCLK↑ to EODX / EODR↓ in word mode
t_d(CH-EH)
Delay from SCLK↑ to EODX / EODR↑ in word mode
t_f(EODX)
EODX fall time
t_f(EODR)
EODR fall time
t_d(CH-EL)
Delay from SCLK↑ to EODX / EODR↓ in byte mode
t_d(CH-EH)
Delay from SCLK↑ to EODX / EODR↑ in byte mode
t_d(MH-SL)
Delay from MSTR CLK↑ to SCLK↓
t_d(MH-SH)
Delay from MSTR CLK↑ to SCLK↑
† _{Typical values are at TA = 25°C.}
SLAS017F − MARCH 1988 − REVISED MAY 1995
TEST CONDITIONS
C_L = 50 pF
C_L = 50 pF
MIN TYP^†
380
45
65
65
MAX
50
50
55
52
52
90
90
90
15
15
100
100
UNIT
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN TYP^†
400
50
50
50
15
15
100
100
65
65
MAX
260
260
316
280
280
UNIT
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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