LM3S628 Datasheet, PDF (269/531 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S628 Microcontroller
8.3.3.1
8.3.3.2
operation. TimerA and TimerB have identical modes, so a single description is given using an n to
reference both.
16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with
an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The
selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR)
register.
When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from
its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from
GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops
counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it
continues counting.
In addition to reloading the count value, the timer generates interrupts and triggers when it reaches
the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is
cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTMIMR, the GPTM
also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The ADC trigger is
enabled by setting the TnOTE bit in the GPTMCTL register.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
The following example shows a variety of configurations for a 16-bit free running timer while using
the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period).
Table 8-3. 16-Bit Timer With Prescaler Configurations
Prescale
#Clock (T c)^a
00000000
1
00000001
2
00000010
3
------------
--
11111101
254
11111110
255
11111111
256
a. Tc is the clock period.
Max Time
1.3107
2.6214
3.9322
--
332.9229
334.2336
335.5443
Units
mS
mS
mS
--
mS
mS
mS
16-Bit Input Edge Count Mode
Note:
For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note: The prescaler is not available in 16-Bit Input Edge Count mode.
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
July 14, 2014
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