LM3S628 Datasheet, PDF (227/531 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S628 Microcontroller
Table 7-3. GPIO Signals (48QFP) (continued)
Pin Name
Pin Number Pin Type Buffer Type^a Description
PA5
22
I/O
TTL
GPIO port A bit 5.
PB0
29
I/O
TTL
GPIO port B bit 0.
PB1
30
I/O
TTL
GPIO port B bit 1.
PB2
33
I/O
TTL
GPIO port B bit 2.
PB3
34
I/O
TTL
GPIO port B bit 3.
PB4
44
I/O
TTL
GPIO port B bit 4.
PB5
43
I/O
TTL
GPIO port B bit 5.
PB6
42
I/O
TTL
GPIO port B bit 6.
PB7
41
I/O
TTL
GPIO port B bit 7.
PC0
40
I/O
TTL
GPIO port C bit 0.
PC1
39
I/O
TTL
GPIO port C bit 1.
PC2
38
I/O
TTL
GPIO port C bit 2.
PC3
37
I/O
TTL
GPIO port C bit 3.
PC4
14
I/O
TTL
GPIO port C bit 4.
PC5
13
I/O
TTL
GPIO port C bit 5.
PC6
12
I/O
TTL
GPIO port C bit 6.
PC7
11
I/O
TTL
GPIO port C bit 7.
PD0
25
I/O
TTL
GPIO port D bit 0.
PD1
26
I/O
TTL
GPIO port D bit 1.
PD2
27
I/O
TTL
GPIO port D bit 2.
PD3
28
I/O
TTL
GPIO port D bit 3.
PE0
35
I/O
TTL
GPIO port E bit 0.
PE1
36
I/O
TTL
GPIO port E bit 1.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
7.3 Functional Description
Important: All GPIO pins are inputs by default (GPIODIR=0 and GPIOAFSEL=0), with the exception
of the five JTAG pins (PB7 and PC[3:0]). The JTAG pins default to their JTAG
functionality (GPIOAFSEL=1). A Power-On-Reset (POR) or asserting an external reset
(RST) puts both groups of pins back to their default state.
While debugging systems where PB7 is being used as a GPIO, care must be taken to
ensure that a Low value is not applied to the pin when the part is reset. Because PB7
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
7-2 on page 228). The LM3S628 microcontroller contains five ports and thus five of these physical
GPIO blocks.
July 14, 2014
227
Texas Instruments-Production Data