UCC5350SB Datasheet, PDF (26/35 Pages) Texas Instruments – 3-kVRMS Single-Channel Isolated Gate Driver with 8-V UVLO

UCC5350SB
SLLSF39 – SEPTEMBER 2017
11 Layout
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11.1 Layout Guidelines
Designers must pay close attention to PCB layout to achieve optimum performance for the UCC5350SB. Some
key guidelines are:
• Component placement:
– Low-ESR and low-ESL capacitors must be connected close to the device between the V_CC1 and GND1
pins and between the V_CC2 and V_EE2 pins to bypass noise and to support high peak currents when turning
on the external power transistor.
– To avoid large negative transients on the V_EE2 pins connected to the switch node, the parasitic
inductances between the source of the top transistor and the source of the bottom transistor must be
minimized.
• Grounding considerations:
– Limiting the high peak currents that charge and discharge the transistor gates to a minimal physical area
is essential. This limitation decreases the loop inductance and minimizes noise on the gate terminals of
the transistors. The gate driver must be placed as close as possible to the transistors.
• High-voltage considerations:
– To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces
or copper below the driver device. A PCB cutout or groove is recommended in order to prevent
contamination that may compromise the UCC5350SB’s isolation performance.
• Thermal considerations:
– A large amount of power may be dissipated by the UCC5350SB if the driving voltage is high, the load is
heavy, or the switching frequency is high (for more information, see the Estimate Gate-Driver Power Loss
section). Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction-to-
board thermal impedance (θ_JB).
– Increasing the PCB copper connecting to the V_CC2, GND1, and V_EE2 pins is recommended, with priority on
maximizing the connection to V_EE2. However, the previously mentioned high-voltage PCB considerations
must be maintained.
– If the system has multiple layers, TI also recommends connecting the V_CC2 and V_EE2 pins to internal
ground or power planes through multiple vias of adequate size. These vias should be located close to the
IC pins to maximize thermal conductivity. However, keep in mind that no traces or coppers from different
high voltage planes are overlapping.
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