UCC5350SB Datasheet, PDF (1/35 Pages) Texas Instruments – 3-kVRMS Single-Channel Isolated Gate Driver with 8-V UVLO

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UCC5350SB
SLLSF39 – SEPTEMBER 2017
UCC5350SB 3-kV_RMS Single-Channel Isolated Gate Driver with 8-V UVLO
1 Features
2 Applications
•1 Single Channel Split Output Gate Driver
• 8.5-A Peak Source, 10-A Peak Sink Output
• 8-V Under Voltage Lockout
• Switching Parameters:
– 65-ns Typical Propagation Delay
– 20-ns Maximum Pulse-Width Distortion
• 100-kV/μs Minimum Common-Mode Transient
Immunity (CMTI)
• 3-V to 15-V Input Supply Voltage
• 9.5-V to 33-V Output Driver Supply Voltage
• Negative Voltage Handling on Input Pins (–5 V)
• Isolation Surge Withstand Voltage: 4242 V_PK
• Safety-Related Certifications:
– 4242-V_PK Isolation per DIN V VDE V 0884-10
(Planned)
– 3000-V_RMS Isolation for 1 Minute per UL 1577
(Planned)
– CSA Component Acceptance Notice 5A, IEC
60950-1 Standard (Planned)
– CQC Certification per GB4943.1-2011
(Planned)
• 4-kV ESD (HBM) on All Pins
• CMOS Inputs
• 8-pin Narrow Body SOIC Package
• Operating Temperature: –40°C to +125°C
Ambient
• Industrial Motor-Control Drives
• Industrial Power Supplies
• Solar Inverters
• HEV and EV Power Modules
• Induction Heating
3 Description
The UCC5350SB is a single-channel, isolated IGBT,
SiC, and MOSFET gate driver with split-outputs and
superior isolation ratings.
The UCC5350SB is available in an 8-pin SOIC (D)
package. This package has a creepage and
clearance of 4 mm and can support isolation voltage
up to 3 kV_RMS, which is good for applications where
basic isolation is needed. With its split-output and 8-V
UVLO this device is a good fit for motor drives and
industrial power supplies.
The UCC5350SB option provides a split output that
can be used to control the rise and fall times of the
driver.
Compared to an optocoupler, the UCC5350SB has
lower part-to-part skew, lower propagation delay,
higher operating temperature, and higher CMTI.
PART
NUMBER
UCC5350SB
Device Information⁽¹⁾
PACKAGE
BODY SIZE (NOM)
D SOIC (8)
4.90 mm x 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
5 V _VCC1
IN+
IN±
Functional Block Diagram
VCC2 ^{15 V}
VCC2
UVLO
and
Input
Logic
UVLO,
Level
Shift
texatnd
Control
Logic
VOUTH
VOUTL
Rest of
Circuit
GND1
VEE2
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.