BQ27425-G2_14 Datasheet, PDF (26/35 Pages) Texas Instruments – System-Side Impedance Track™ Fuel Gauge With Integrated Sense Resistor

bq27425-G2
SLUSB23A – OCTOBER 2012 – REVISED FEBRUARY 2013
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I²C Command Waiting Time
To ensure proper operation at 400 kHz, a t_(BUF) ≥ 66 μs bus-free waiting time must be inserted between all
packets addressed to the bq27425-G2. In addition, if the SCL clock frequency (f_SCL) is > 100 kHz, use individual
1-byte write commands for proper data flow control. The following diagram shows the standard waiting time
required between issuing the control subcommand the reading the status result. For read-write standard
command, a minimum of 2 seconds is required to get the result updated. For read-only standard commands,
there is no waiting time required, but the host must not issue any standard command more than two times per
second. Otherwise, the gauge could result in a reset issue due to the expiration of the watchdog timer.
S ADDR [6:0] 0 A CMD [7:0] A DATA [7:0] A P 66ms
S ADDR [6:0] 0 A CMD [7:0] A DATA [7:0] A P 66ms
S ADDR [6:0] 0 A CMD [7:0] A Sr ADDR [6:0] 1 A DATA [7:0] A DATA [7:0]
Waiting time inserted between two 1-byte write packets for a subcommand and reading results
(required for 100 kHz < f_SCL £ 400 kHz)
NP
66ms
S ADDR [6:0] 0 A CMD [7:0] A DATA [7:0] A DATA [7:0] A P 66ms
S ADDR [6:0] 0 A CMD [7:0] A Sr ADDR [6:0] 1 A DATA [7:0] A DATA [7:0] N P
Waiting time inserted between incremental 2-byte write packet for a subcommand and reading results
(acceptable for f_SCL £ 100 kHz)
66ms
S ADDR [6:0] 0 A CMD [7:0] A Sr ADDR [6:0] 1 A DATA [7:0] A DATA [7:0] A
DATA [7:0] A DATA [7:0] N P 66ms
Waiting time inserted after incremental read
I²C Clock Stretching
A clock stretch can occur during all modes of fuel gauge operation. In SLEEP and HIBERNATE modes, a short
clock stretch occurs on all I²C traffic as the device must wake-up to process the packet. In the other modes (
INITIALIZATION , NORMAL) clock stretching only occurs for packets addressed for the fuel gauge. The majority
of clock stretch periods are small as the I²C interface performs normal data flow control. However, less frequent
yet more significant clock stretch periods may occur as blocks of NVM are updated. The following table
summarizes the approximate clock stretch duration for various fuel gauge operating conditions.
Gauging Mode
SLEEP
HIBERNATE
INITIALIZATION
NORMAL
Operating Condition / Comment
Clock stretch occurs at the beginning of all traffic as the device wakes up.
Clock stretch occurs within the packet for flow control (after a start bit, ACK or first data bit).
Normal Ra table NVM updates.
NVM block writes.
Restored NVM block write after loss of power.
End of discharge Ra table NVM update.
Approximate
Duration
≤ 4 ms
≤ 4 ms
24 ms
72 ms
116 ms
144 ms
26
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