ADC12DL066_15 Datasheet, PDF (26/33 Pages) Texas Instruments – 450 MHz Input Bandwidth A/D Converter

ADC12DL066
SNAS188G – FEBRUARY 2004 – REVISED FEBRUARY 2013
www.ti.com
COMMON
GROUND
PLANE
OSC
Clock line should be short
and cross no other lines.
LATCH
All Analog Components mounted
over Analog are of Ground Plane
6 x 100:
Xfmr/Amplifier
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
All Digital components
mounted over Digital area
of Ground Plane
1
2
3
4
5
6
Driving source
located close to
7
converter Single Ground entry for all
8
Reference Components
9
10
11
12
13
14
15
16
Analog power line should be routed
away from Digital power trace.
VIN B-
VIN B+
AGND
V_RM B
V_RP B
V_RN B
V_REF
AGND
V_A
ADC12DL066
AGND
INT/EXT REF
V_RN A
V_RP A
V_RM A
VIN A+
VIN A-
48
V_{D 47}
DB5
46
DB4
45
DB3
44
DB2
43
DB1
42
DB0
41
OEB
40
DR GND
39
DA11
38
DA10
37
DA9
36
DA8
35
DA7
34
DA6
33
V_D
6 x 100:
LATCH
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Digital power line should be routed
away from analog power trace.
Ground entry points
close to ground pins.
Figure 35. Example of a Suitable Layout
Since digital switching transients are composed largely of high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area
is more important than is total ground plane volume.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in
high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to
keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the
generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause
problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to
degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.
Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the
signal path through all components should form a straight line wherever possible.
Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit
in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies
beside each other.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to
the reference input pin and ground should be connected to a very clean point in the ground plane.
Figure 35 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference
components, etc.) should be placed in the analog area of the board. All digital circuitry and I/O lines should be
placed in the digital area of the board. The ADC12DL066 should be between these two areas. Furthermore, all
components in the reference circuitry and the input signal chain that are connected to ground should be
connected together with short traces and enter the ground plane at a single, quiet point. All ground connections
should have a low inductance path to ground.
26
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