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VCA810_16 Datasheet, PDF (25/40 Pages) Texas Instruments – VCA810 High Gain Adjust Range, Wideband and Variable Gain Amplifier
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Application Information (continued)
VCA810
SBOS275G – JUNE 2003 – REVISED DECEMBER 2015
5
4
3
2
1
0
I
-1
-2
-3
-4
-5
0.001
0.01
II
0.1
1
VIN/VR Voltage Ratio
III
10
100
Figure 40. Test Result for LOG Amp for VR = −100 mV
The above VOL expression reflects a circuit gain introduced by the presence of R1 and R2. This feature adds a
convenient scaling control to the circuit. However, a practical matter sets a minimum level for this gain. The
voltage divider formed by R1 and R2 attenuates the voltage supplied to the VC terminal by the operational
amplifier. This attenuation must be great enough to prevent any possibility of an overload voltage at the VC
terminal. Such an overload saturates the VCA810 gain-control circuitry, reducing the amplifier’s gain. For the
feedback connection of Figure 39, this overload condition permits a circuit latch. To prevent this, choose R1 and
R2 to ensure that the operational amplifier cannot possibly deliver a more negative input than −2.5 V to the VC
terminal.
Figure 40 exhibits three zones of operation described below:
Zone I: VC > 0 V. The VCA810 is operating in full attenuation (−80 dB). The noninverting input of the OPA820
will see ∼0 V. VOL is going to be the integration of the input signal.
Zone II: −2 V < VC < 0 V. The VCA810 is in its normal operating mode, creating the log relationship in
Equation 7.
Zone III: VC < −2 V. The VCA810 control pin is out of range, and some measure should be taken so that it does
not exceed –2.5 V. A limiting action could be achieved by using a voltage limiting amplifier.
9.1.6 Voltage-Controlled Low-Pass Filter
In the circuit of Figure 41, the VCA810 serves as the variable-gain element of a voltage-controlled low-pass filter.
This section discusses how this implementation expands the circuit voltage swing capability over that normally
achieved with the equivalent multiplier implementation. The circuit response pole responds to control voltage VC,
according to the relationship in Equation 8:
G
f=
P 2pR2C
where
• G = 10-2 (VC + 1)
(8)
With the components shown, the circuit provides a linear variation of the low-pass cutoff from 300 Hz to 1 MHz.
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