BQ25505 Datasheet, PDF (25/34 Pages) Texas Instruments – Ultra Low Power Boost Charger with Battery Management and Autonomous Power

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bq25505
SLUSBJ3B – AUGUST 2013 – REVISED JANUARY 2014
LAYOUT CONSIDERATIONS
As for all switching power supplies, the PCB layout is an important step in the design, especially at high peak
currents and high switching frequencies. If the layout is not carefully done, the boost charger could show stability
problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the
power ground paths. The input and output capacitors as well as the inductors should be placed as close as
possible to the IC. For the boost charger, first priority are the output capacitors, including the 0.1 uF bypass
capacitor (CBYP), followed by CSTOR, which should be placed as close as possible between VSTOR, pin 19,
and VSS, pin 1. Next, the input capacitor, CIN, should be placed as close as possible between VIN_DC, pin 2,
and VSS, pin 1. Last in priority is the boost charger inductor, L1, which should be placed close to LBOOST, pin
20, and VIN_DC, pin 2. It is best to use vias and bottom traces for connecting the inductors to their respective
pins instead of the capacitors.
To minimize noise pickup by the high impedance voltage setting nodes (VBAT_OV, OK_PROG, OK_HYST), the
external resistors should be placed so that the traces connecting the midpoints of each divider to their respective
pins are as short as possible. When laying out the non-power ground return paths (e.g. from resistors and
CREF), it is recommended to use short traces as well, separated from the power ground traces and connected to
VSS pin 15. This avoids ground shift problems, which can occur due to superimposition of power ground current
and control ground current. The PowerPad should not be used as a power ground return path.
The remaining pins are either NC pins, that should be connected to the PowerPad as shown below, or digital
signals with minimal layout restrictions. See the EVM user's guide for an example layout (SLUUAA8).
In order to maximize efficiency at light load, the use of voltage level setting resistors > 1 MΩ is recommended. In
addition, the sample and hold circuit output capacitor on VREF_SAMP must hold the voltage for 16 s. During
board assembly, contaminants such as solder flux and even some board cleaning agents can leave residue that
may form parasitic resistors across the physical resistors/capacitors and/or from one end of a resistor/capacitor
to ground, especially in humid, fast airflow environments. This can result in the voltage regulation and threshold
levels changing significantly from those expected per the installed components. Therefore, it is highly
recommended that no ground planes be poured near the voltage setting resistors or the sample and hold
capacitor. In addition, the boards must be carefully cleaned, possibly rotated at least once during cleaning, and
then rinsed with de-ionized water until the ionic contamination of that water is well above 50 Mohm. If this is not
feasible, then it is recommended that the sum of the voltage setting resistors be reduced to at least 5X below the
measured ionic contamination.
THERMAL CONSIDERATIONS
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below.
• Improving the power-dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
For more details on how to use the thermal parameters in the Thermal Table, check the Thermal Characteristics
Application Note (SZZA017) and the IC Package Thermal Metrics Application Note (SPRA953).
Copyright © 2013–2014, Texas Instruments Incorporated
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