TM4C1237H6PZ Datasheet, PDF (248/1307 Pages) Texas Instruments – Tiva Microcontroller

System Control
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
The bits in this register configure the system clock and oscillators.
Important: Write the RCC register prior to writing the RCC2 register.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type RW, reset 0x0780.3AD1
31
30
29
28
27
26
reserved
ACG
Type RO
RO
RO
RO
RW
RW
Reset
0
0
0
0
0
1
Type
Reset
15
14
reserved
RO
RO
0
0
13
12
11
10
PWRDN reserved BYPASS
RW
RO
RW
RW
1
1
1
0
25
24
SYSDIV
RW
RW
1
1
9
8
XTAL
RW
RW
1
0
23
22
21
20
USESYSDIV
RW
RW
RO
RO
1
0
0
0
7
6
5
4
OSCSRC
RW
RW
RW
RW
1
1
0
1
19
18
reserved
RO
RO
0
0
3
2
reserved
RO
RO
0
0
17
16
RO
RO
0
0
1
0
MOSCDIS
RO
RW
0
1
Bit/Field
31:28
27
26:23
Name
reserved
ACG
SYSDIV
Type
RO
RW
RW
Reset
0x0
0
0xF
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the microcontroller enters a Sleep
or Deep-Sleep mode (respectively).
Value Description
0 The Run-Mode Clock Gating Control (RCGCn) registers are
used when the microcontroller enters a sleep mode.
1 The SCGCn or DCGCn registers are used to control the clocks
distributed to the peripherals when the microcontroller is in a
sleep mode. The SCGCn and DCGCn registers allow unused
peripherals to consume less power when the microcontroller is
in a sleep mode.
The RCGCn registers are always used to control the clocks in Run
mode.
System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS
bit in this register is configured). See Table 5-4 on page 218 for bit
encodings.
If the SYSDIV value is less than MINSYSDIV (see page 413), and the
PLL is being used, then the MINSYSDIV value is used as the divisor.
If the PLL is not being used, the SYSDIV value can be less than
MINSYSDIV.
248
June 12, 2014
Texas Instruments-Production Data