TPS51200-EP_17 Datasheet, PDF (24/35 Pages) Texas Instruments – Sink and Source DDR Termination Regulator

TPS51200-EP
SLUSA48 – JUNE 2016
8.3.6 3.3-V_IN, DDR3 Configuration with LFP
This design example describes a 3.3-V_IN, DDR3 configuration with LFP application.
V_VDDQ = 1.5 V
R1
10 k:
V_VLDOIN = V_VDDQ = 1.5 V
R2
C4
10 k: 1000 pF
TPS51200
1 REFIN
VIN 10
C7
C8
10 PF 10 PF
2 VLDOIN PGOOD 9
R3
100 k:
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3.3 V_IN
C6
4.7 PF
PGOOD
V_VTT = 0.75 V
C1 C2 C3
10 PF 10 PF 10 PF
3 VO
R4⁽¹⁾
4 PGND
GND 8
EN 7
SLP_S3
5 VOSNS REFOUT 6
C9⁽¹⁾
C5
0.1 PF
VTTREF
UDG-08034
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Figure 29. 3.3-V_IN, DDR3 Configuration with LFP
REFERENCE
DESIGNATOR
R1, R2
R3
R4 ⁽¹⁾
C1, C2, C3
C4
C5
C6
C7, C8
C9 ⁽¹⁾
Table 7. 3.3-V_IN, DDR3 Configuration with LFP List of Materials
DESCRIPTION
SPECIFICATION
PART NUMBER
Resistor
10 kΩ
100 kΩ
MANUFACTURER
Capacitor
10 μF, 6.3 V
1000 pF
0.1 μF
4.7 μF, 6.3 V
10 μF, 6.3 V
GRM21BR70J106KE76L
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
Murata
(1) Choose values for R4 and C9 to reduce the parasitic effect of the trace (between VO and the output MLCCs) and the output capacitors
(ESR and ESL).
24
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