TMS34094 Datasheet, PDF (24/38 Pages) Texas Instruments – ISA BUS INTERFACE

TMS34094
ISA BUS INTERFACE
SPVS006A – FEBRUARY 1992 – REVISED JUNE 1992
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) concluded
NO.
PARAMETER
MIN
75 tRSDHHWZ HWRITE disable time after RESDRV high
5tQ
76 tRSDHHRZ HREAD disable time after RESDRV high
5tQ
77 tRSDHHBZ HBS01, HBS23 disable time after RESDRV high
5tQ
78 tRSDHVSZ VGASHAD disable time after RESDRV high
5tQ
79 tRSDHBSZ BSEL3–BSEL0 disable time after RESDRV high
5tQ
80 tRSDHHANV Delay time, HA31–HA5 no longer valid after RESDRV high
5tQ
81 tRSDHCRZ CHRDY disable time after RESDRV high
82 tRSDHIO16Z IO16 disable time after RESDRV high
83 tRSDHM16Z M16 disable time after RESDRV high
84 tIOSSRSDL Setup time, IOSEL2–IOSEL0 valid before RESDRV low
100
85 tBIOSRSDL Setup time, BIOSEN valid before RESDRV low
0
86 tRSDLRSTH Delay time, RESDRV low to RESET high
87 tBIOHRSDL Hold time, BIOSEN valid after RESDRV low
25
88 tRSDLSRTL Delay time, RESDRV low to SSRT low
89 tRSDLCSH Delay time, RESDRV low to HCS high
90 tRSDLHWH Delay time, RESDRV low to HWRITE high
91 tRSDLHRH Delay time, RESDRV low to HREAD high
92 tRSDLHBNZ Delay time, RESDRV low to HBS01, HBS23 driven
93 tRSDLVSL
Delay time, RESDRV low to VGASHAD low
94 tRSDLBSNZ Delay time, RESDRV low to BSEL3–BSEL0 driven
95 tLADSALL
Setup time, LAD31–LAD0 address and status valid before ALTCH low
5
96 tLADVBSV
Delay time, LAD31–LAD0 address and status valid to BSEL3–BSEL0 valid
0
97 tALHBSV
Delay time, BSEL3–BSEL0 transparently decodes LAD31–LAD0 after the later
of ALTCH high, RAS high
98 tLADHALL
Hold time, LAD31–LAD0 address and status valid after ALTCH low
5
99 tSFLLCK1L Setup time, SF low before LCLK1 low
5
100 tCASSLCK1L Setup time, CAS2 low before LCLK1 low
5
101 tLCK2LSRTH Delay time, LCLK2 low to SSRT high
0
102 tLCK2LSRTL Delay time, LCLK2 low to SSRT low
5
103 tAENVISL
Delay time, AEN valid to I/O strobe low
95
104 tSBSISL
Setup time, SBHE valid before I/O strobe low
85
105 tSASISL
Setup time, SA10–SA0 valid before I/O strobe low
85
106 tSBSMSL
Setup time, SBHE valid before MEM strobe low
22
107 tSASMSL
Setup time, SA19–SA0 valid before MEM strobe low
22
108 tAENVISH
Delay time, AEN valid after I/O stobe high
28
109 tSBHISH
Hold time, SBHE valid after I/O stobe high
30
110 tSAHISH
Hold time, SA10–SA0 valid after I/O strobe high
30
111 tSBHMSH
Hold time, SBHE valid after MEM stobe high
30
112 tSAHMSH
Hold time, SA19–SA0 valid after MEM strobe high
30
MAX
5tQ + 50
5tQ + 50
5tQ + 50
5tQ + 45
5tQ + 40
5tQ + 50
5tQ
5tQ
5tQ
50
60
60
55
55
90
90
45
25
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30 ns
ns
ns
ns
25 ns
45 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
24
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