TMS34094 Datasheet, PDF (17/38 Pages) Texas Instruments – ISA BUS INTERFACE

TMS34094
ISA BUS INTERFACE
SPVS006A – FEBRUARY 1992 – REVISED JUNE 1992
split serial register transfer support
The TMS34020 generates split serial register transfer cycles to VRAM when the SRT bit in the DPYCTL register
is set. During horizontal blanking, a regular transfer cycle is generated to transfer the next row of pixel data into
the serial register. This is immediately followed by a split serial register transfer cycle to replace the inactive half
row of serial register data with new undisplayed data, rather than those most recently displayed.
Most VRAM require a shift clock pulse between the normal serial register transfer and the split register transfer
to ensure that the tap point presented during the normal serial transfer is not overwritten by the tap point of the
split shift register transfer. The TMS34094 provides an SSRT signal between the rising edge of RAS at the end
of the normal transfer cycle and the next falling edge of LCLK2. This signal may be used to indicate to the
TLC34075 (or other SCLK generating circuit) that a shift clock pulse must be generated.
local address decode
The TMS34094 provides four active low bank select signals. BSEL0–BSEL3 are typically gated externally with
RAS to form four separate row-address strobes to four banks of memory devices.
Each bank select control mechanism is defined by the contents of five registers:
• Two 16-bit Bank Select Mask Registers. These registers form a 32-bit value to define which bits of the
address output on LAD31–LAD0 are to be ignored when determining whether a bank has been selected.
A bit set to 0 in a mask register corresponds to an address bit which is ignored.
• Two 16-bit Bank Select Address Registers. These registers form a 32-bit quantity which determines the
value of the unmasked bits of the address output on LAD31–LAD0 that should select the bank.
• The values of BVEN3–BVEN0, BDRD3–BDRD0, and RM1–RM0 in the BKCTL register determine how the
bank should be selected for VRAM write mask or color register load cycles, and DRAM refresh cycles.
To place a bank of RAM into TMS34020 memory space without aliasing, use the following formula to determine
the BKMSK value:
BKMSKx = 0FFFFFFFFh – (bank size in bits) + 1
Therefore, the BKMSKx value for a 1MByte bank of RAM connected to BSEL1 is:
BKMSK1 = 0FFFFFFFFh – 0800000h + 1 = 0FF800000h
For this setting, the bank select mechanism will only compare BKAD1 bits 31 through 23 with LAD bus address
bits 31 through 23. BKAD1 bits 22 through 0 and LAD address bits 22 through 0 will be ignored.
BSEL0–BSEL3 are inactive during a VGA shadow palette access. A BSELx signal will only go active during
VRAM write-mask-load cycles and color-register-load cycles if its corresponding BVEN bit is set. The value of
the BPNT field in BKCTL is used as an index into the BKAD0–BKAD3 and BKMSK0–BKMSK3 registers. Data
accesses to the indexed register are performed via the BKPORT register.
Bank 3 is unconditionally enabled for all accesses except VGA shadow reads/writes after reset. All other banks
are disabled except for memory refresh when ABE is set to 0. Bank select control must be initialized by setting
ABE in MODECTL to 1.
Host write accesses to BKAD3–BKAD0 or BKMSK3–BKMSK0 may cause improper decoding of ongoing
TMS34020 local bus cycles. Do not write any BKAD3–BKAD0 or BKMSK3–BKMSK0 register while the
TMS34020 is performing any operation which could be adversely affected by improper address decoding,
including execution of code. When multiple banks are programmed to respond to the same LAD bus address,
the TMS34094 will assert only the lowest-numbered BSELn output.
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