THS770012_14 Datasheet, PDF (24/36 Pages) Texas Instruments – Broadband, Fully-Differential, 14-/16-Bit ADC Driver Amplifier

THS770012
SLOS669C – FEBRUARY 2010 – REVISED JANUARY 2012
EVM AND LAYOUT RECOMMENDATIONS
www.ti.com
Figure 37 is the THS770012RGE EVM schematic, and Figure 43 through Figure 46 show the layout details of the
EVM PCB. Table 5 is the bill of materials for the EVM as supplied from TI. It is recommended to follow the layout
of the external components as close as possible to the amplifier, ground plane construction, and power routing.
General layout guidelines are:
1. Place a 2.2µF to 10µF capacitor on each supply pin within 2 inches from the device. It can be shared among
other op amps.
2. Place a 0.01µF to 0.1µF capacitor on each supply pin to ground as close as possible to the device.
Placement within 1mm of the device supply pins ensures best performance.
3. Keep output traces as short as possible to minimize parasitic capacitance and inductance. Doing so reduces
unwanted characteristics such as peaking in the frequency response, overshoot, and ringing in the pulse
response, and results in a more stable design.
4. To reduce parasitic capacitance, ground plane and power-supply planes should be removed from device
output pins.
5. The V_OCM pin must be biased to a voltage between 2.25V to 2.75V for proper operation. Place a 0.1µF to
0.22µF capacitor to ground as close as possible to the device to prevent noise coupling into the
common-mode.
6. For best performance, drive circuits and loads should be balanced and biased to keep the input and output
common-mode voltage between 2.25V to 2.75V. AC-coupling is a simple way to achieve this performance.
7. The THS770012 is provided in a thermally enhanced PowerPAD™ package. The package is constructed
using a downset leadframe on which the die is mounted. This arrangement results in low thermal resistance
to the thermal pad on the underside of the package. Excellent thermal performance can be achieved by
following the guidelines in TI application reports SLMA002, PowerPAD™ Thermally-Enhanced Package and
SLMA004, PowerPAD™ Made Easy. For proper operation, the thermal pad on the bottom of the device must
be tied to the same voltage potential as the GND pin on the device.
Figure 43. EVM Layout: Top Layer
Figure 44. EVM Layout: Bottom Layer
24
Submit Documentation Feedback
Product Folder Link(s): THS770012
Copyright © 2010–2012, Texas Instruments Incorporated