OPA1641-Q1 Datasheet, PDF (24/31 Pages) Texas Instruments – SoundPlus JFET-Input, Automotive-Grade, Audio Operational Amplifiers

OPA1641-Q1, OPA1642-Q1
SBOS791 – JUNE 2017
10 Layout
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10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the op
amp itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local
to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically
separate digital and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output
traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better
as opposed to in parallel with the noisy trace.
• Place the external components as close as possible to the device. As shown in Figure 39, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• TI recommends cleaning the PCB following board assembly for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB
assembly to remove moisture introduced into the device packaging during the cleaning process. A low
temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
VIN
RG
+
RF
VOUT
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
RG
GND
VIN
RF
N/C
±IN
+IN
V±
N/C
V+
OUTPUT
N/C
VS+
GND
Use low-ESR, ceramic
bypass capacitor
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
VOUT
Ground (GND) plane on another layer
Figure 39. OPA1641-Q1 Layout Example
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