LM3S5P56 Datasheet, PDF (24/1147 Pages) Texas Instruments – Stellaris LM3S5P56 Microcontroller

Table of Contents
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ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 590
ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 592
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 594
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 594
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 595
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 595
ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 597
ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 597
ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 598
ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 598
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 600
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 601
ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 602
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 603
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 604
ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 609
ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 609
ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 609
ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 609
ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 609
ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 609
ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 609
ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 609
ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 612
ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 612
ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 612
ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 612
ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 612
ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 612
ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 612
ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 612
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 613
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 625
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 627
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 630
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 632
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 633
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 634
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 635
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 637
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 640
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 642
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 645
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 648
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 651
Register 14: UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 653
Register 15: UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 654
Register 16: UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 655
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July 03, 2014
Texas Instruments-Production Data