LM3S1P51 Datasheet, PDF (24/1033 Pages) Texas Instruments – Stellaris® LM3S1P51 Microcontroller

Table of Contents
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 663
UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 664
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 665
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 666
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 667
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 668
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 669
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 670
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 671
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 672
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 673
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 674
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 675
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 676
Synchronous Serial Interface (SSI) ............................................................................................ 677
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 692
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 694
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 696
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 697
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 699
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 700
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 701
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 703
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 705
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 706
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 707
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 708
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 709
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 710
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 711
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 712
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 713
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 714
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 715
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 716
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 717
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 718
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 719
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 736
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 737
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 742
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 743
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 744
Register 6: I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 745
Register 7: I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 746
Register 8: I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 747
Register 9: I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 748
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January 21, 2012
Texas Instruments-Production Data