LM3S1P51 Datasheet, PDF (221/1033 Pages) Texas Instruments – Stellaris® LM3S1P51 Microcontroller

Stellaris^® LM3S1P51 Microcontroller
Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
DSDIVORIDE
reserved
Type RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DSOSCSRC
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:29
28:23
Name
reserved
DSDIVORIDE
Type
RO
R/W
Reset
0x0
0x0F
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Divider Field Override
If Deep-Sleep mode is enabled when the PLL is running, the PLL is
disabled. This 6-bit field contains a system divider field that overrides
the SYSDIV field in the RCC register or the SYSDIV2 field in the RCC2
register during Deep Sleep. This divider is applied to the source selected
by the DSOSCSRC field.
Value Description
0x0 /1
0x1 /2
0x2 /3
0x3 /4
... ...
0x3F /64
22:7
reserved
RO
0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
January 21, 2012
221
Texas Instruments-Production Data