ADC08D500 Datasheet, PDF (24/48 Pages) Analog Devices – High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter

ADC08D500
SNAS274F – MAY 2005 – REVISED APRIL 2013
www.ti.com
CalDly (pin 127) is used to select one of two delay times after the application of power to the start of calibration.
This calibration delay is 2²⁵ clock cycles (about 67.2 ms at 500 MSPS) with CalDly low, or 2³¹ clock cycles (about
4.3 seconds at 500 MSPS) with CalDly high. These delay values allow the power supply to come up and stabilize
before calibration takes place. If the PD pin is high upon power-up, the calibration delay counter will be disabled
until the PD pin is brought low. Therefore, holding the PD pin high during power up will further delay the start of
the power-up calibration cycle. The best setting of the CalDly pin depends upon the power-on settling time of the
power supply.
The CalRun output is high whenever the calibration procedure is running. This is true whether the calibration is
done at power-up or on-command.
Acquiring the Input
Data is acquired at the falling edge of CLK+ (pin 18) and the digital equivalent of that data is available at the
digital outputs 13 clock cycles later for the DI and DQ output buses and 14 clock cycles later for the DId and DQd
output buses. There is an additional internal delay called t_OD before the data is available at the outputs. See the
Timing Diagram. The ADC08D500 will convert as long as the clock signal is present. The fully differential
comparator design and the innovative design of the sample-and-hold amplifier, together with self calibration,
enables a very flat SINAD/ENOB response beyond 500 MHz. The ADC08D500 output data signaling is LVDS
and the output format is offset binary.
Control Modes
Much of the user control can be accomplished with several control pins that are provided. Examples include
initiation of the calibration cycle, power down mode and full scale range setting. However, the ADC08D500 also
provides an Extended Control mode whereby a serial interface is used to access register-based control of
several advanced features. The Extended Control mode is not intended to be enabled and disabled dynamically.
Rather, the user is expected to employ either the normal control mode or the Extended Control mode at all times.
When the device is in the Extended Control mode, pin-based control of several features is replaced with register-
based control and those pin-based controls are disabled. These pins are OutV (pin 3), OutEdge/DDR (pin 4),
FSR (pin 14) and CalDly/DES (pin 127). See NORMAL/EXTENDED CONTROL for details on the Extended
Control mode.
The Analog Inputs
The ADC08D500 must be driven with a differential input signal. Operation with a single-ended signal is not
recommended. It is important that the inputs either be a.c. coupled to the inputs with the V_CMO pin grounded or
d.c. coupled with the V_CMO pin not grounded and an input common mode voltage equal to the V_CMO output.
Two full-scale range settings are provided with pin 14 (FSR). A high on pin 14 causes an input full-scale range
setting of 870 mV_P-P, while grounding pin 14 causes an input full-scale range setting of 650 mV_P-P. The full-scale
range setting operates equally on both ADCs.
In the Extended Control mode, the full-scale input range can be set to values between 560 mV_P-P and 840 mV_P-P
through a serial interface. See THE ANALOG INPUT.
Clocking
The ADC08D500 must be driven with an a.c. coupled, differential clock signal. THE CLOCK INPUTS describes
the use of the clock input pins. A differential LVDS output clock is available for use in latching the ADC output
data into whatever receives that data.
The ADC08D500 offers options for input and output clocking. These options include a choice of Dual Edge
Sampling (DES) or interleaved mode where the ADC08D500 performs as a single device converting at twice the
input clock rate and a choice of which DCLK edge the output data transitions on and choice of Single Data Rate
(SDR) or Double Data Rate (DDR) outputs.
The ADC08D500 also has the option to use a duty cycle corrected clock receiver as part of the input clock
circuit. This feature is enabled by default and provides improved ADC clocking, especially in the Dual-Edge
Sampling mode (DES). This circuitry allows the ADC to be clocked with a signal source having a duty cycle ratio
of 80 / 20 % (worst case) for both the normal and the Dual Edge Sampling modes.
24
Submit Documentation Feedback
Product Folder Links: ADC08D500
Copyright © 2005–2013, Texas Instruments Incorporated