ADC08D500 Datasheet, PDF (17/48 Pages) Analog Devices – High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter

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ADC08D500
SNAS274F – MAY 2005 – REVISED APRIL 2013
CLK
DCLK_RST
DCLK+
Synchronizing Edge
t_RH
t_RPW
t_RS
t_AD
CLK
DCLK_RST
DCLK+
Figure 6. Clock Reset Timing in DDR Mode
Synchronizing Edge
t_RH
t_RS
t_SD
t_RPW
OUTEDGE
Figure 7. Clock Reset Timing in SDR Mode with OUTEDGE Low
Synchronizing Edge
CLK
DCLK_RST
t_RH
t_RS
t_SD
t_RPW
DCLK+
OUTEDGE
Figure 8. Clock Reset Timing in SDR Mode with OUTEDGE High
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