TMS320DM6437_15 Datasheet, PDF (230/306 Pages) Texas Instruments – Digital Media Processor

TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 6-44. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to PCLK and VPBECLK⁽¹⁾ (see Figure 6-25)
NO.
PARAMETER
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
MIN
MAX
UNIT
11
t_{d(PCLK-VCTLV)}
12
t_{d(PCLK-VCTLIV)}
13
t_{d(PCLK-VDATAV)}
14
t_{d(PCLK-VDATAIV)}
29
t_{d(VPBECLK-VCTLV)}
30
t_{d(VPBECLK-VCTLIV)}
31
t_{d(VPBECLK-VDATAV)}
32
t_{d(VPBECLK-VDATAIV)}
Delay time, PCLK edge to VCTL valid
Delay time, PCLK edge to VCTL invalid
Delay time, PCLK edge to VDATA valid
Delay time, PCLK edge to VDATA invalid
Delay time, VPBECLK rising edge to VCTL valid
Delay time, VPBECLK rising edge to VCTL invalid
Delay time, VPBECLK rising edge to VDATA valid
Delay time, VPBECLK rising edge to VDATA invalid
14 ns
2.5
ns
14 ns
2.5
ns
14 ns
2.5
ns
14 ns
2.5
ns
(1) PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising
edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.
VPBECLK
PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
VCTL^(A)
VDATA^(B)
11, 29
13, 31
12, 30
14, 32
A. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE
B. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]
Figure 6-25. VPBE Output Timing With Respect to PCLK and VPBECLK
230 Peripheral Information and Electrical Specifications
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