TMS320DM6437_15 Datasheet, PDF (2/306 Pages) Texas Instruments – Digital Media Processor

TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
• Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
• Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
• One 64-Bit Watch Dog Timer
• Two UARTs (One with RTS and CTS Flow
Control)
• Master/Slave Inter-Integrated Circuit (I²C
Bus™)
• Two Multichannel Buffered Serial Ports
(McBSPs)
– I2S and TDM
– AC97 Audio Codec Interface
– SPI
– Standard Voice Codec Interface (AIC12)
– Telecom Interfaces – ST-Bus, H-100
– 128 Channel Mode
• Multichannel Audio Serial Port (McASP0)
– Four Serializers and SPDIF (DIT) Mode
• 16-Bit Host-Port Interface (HPI)
• High-End CAN Controller (HECC)
• 32-Bit 33-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
• 10/100 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
www.ti.com
– Supports Media Independent Interface (MII)
– Management Data I/O (MDIO) Module
• VLYNQ™ Interface (FPGA Interface)
• Three Pulse Width Modulator (PWM) Outputs
• On-Chip ROM Bootloader
• Individual Power-Savings Modes
• Flexible PLL Clock Generators
• IEEE-1149.1 (JTAG™)
Boundary-Scan-Compatible
• Up to 111 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
• Packages:
– 361-Pin Pb-Free PBGA Package
(ZWT Suffix), 0.8-mm Ball Pitch
– 376-Pin Plastic BGA Package
(ZDU Suffix), 1.0-mm Ball Pitch
• 0.09-µm/6-Level Cu Metal Process (CMOS)
• 3.3-V and 1.8-V I/O, 1.2-V Internal
(-7/-6/-5/-4/-L/-Q6/-Q5/-Q4)
• 3.3-V and 1.8-V I/O, 1.05-V Internal
(-7/-6/-5/-4/-L/-Q5)
• Applications
– Digital Media
– Networked Media Encode/Decode
– Video Imaging
2
TMS320DM6437 Digital Media Processor
Submit Documentation Feedback