UCD7242-EP Datasheet, PDF (23/36 Pages) Texas Instruments – Digital Dual Synchronous-Buck Power Driver

UCD7242-EP
www.ti.com
SLVSBY2 – OCTOBER 2013
The term in this equation multiplied by the esr gives the ripple voltage component due to esr and the term
multiplied by 1/C gives the ripple voltage component due to the change in charge on the capacitor plates. In the
case were the esr component dominates the peak to peak output voltage can be approximated as:
V_PPesr ≉ ΔI × esr
(17)
(17)
When the charge term dominates the peak to peak voltage ripple becomes:
V_PPQ
»
DI
8 ´ C ´ ¦_s
(18)
It is tempting to simply add these two results together for the case where the voltage ripple is significantly
influenced by both the capacitance and the esr. However, this will yield an overly pessimistic result, in that it
does not account for the phase difference between these terms.
Using the ripple voltage equations and the RMS current equation should give a design that safely meets the
steady state output requirements. However, additional capacitance is often needed to meet transient
requirements and the specific local decoupling requirements of any IC that is being powered off of this voltage.
This is not just a function of the capacitor bank but also the dynamics of the control loop. See the UCD9240
Compensation Cookbook for additional details.
DECOUPLING
It is necessary that V_GG and BP3 have their own local capacitance as physically close as possible to these pins.
The V_GG capacitor should be connected as close as possible to pin 5 and PGND with a 4.7μF ceramic capacitor.
The BP3 capacitor should be connected as close as possible to pin 22 and AGND with a 1μF ceramic capacitor.
The UCD7242 also supports the ability to operate from input voltages down to 2.2V. In these cases an additional
supply rail must be connected to V_GG and VGG_DIS must be shorted to V_GG. Potential external bias supply
generators for low V_IN operation: TPS63000, TPS61220. The amount of current required for this supply is
dependant on the V_GG voltage, the switching frequency and the number of active channels used in the UCD7242.
When both sides are active, use Figure 11: V_GG Supply Current with 2 Rails Operating for current draw
estimates. If only one side is active, use Figure 10: V_GG Supply Current with 1 Rail Operating and 1 Rail Off.
CURRENT SENSE
An appropriate resistor must be connected to the current sense output pins to convert the I_MON current to a
voltage. In the case of the UCD9XXX digital controllers, these parts have a full scale current monitor range of 0V
to 2V. It is desirable to maximize this range to make full use of the current monitoring resolution inside the
controller. In order to ensure that current sensing will occur all the way to I_MAX=10A a 1.8V target is chosen. In
this case a resistor 9.09kΩ would work.
R_{MO N}
=
V_MON
I_MAX
´ 20 ^{m A}
A
(19)
In some applications it may be necessary to filter the I_MON signal. The UCD7242 I_MON pin is a current source
output, so a capacitor to ground in parallel with the current-to-voltage conversion resistor is all that is required.
As a rule of thumb, placing the corner frequency of the filter at 20% of the switching frequency should be
sufficient.
For example, if the switching frequency is 500kHz or higher the ripple frequency will be easily rejected with a
corner frequency of approximately 100kHz. With a 100kHz pole point, the filter time constant is 1.6µs. A fast
current transient should be detected within 4.8µs.
1
C_MON = _{2 × p × RMON × 20%×fs}
(20)
20A Power Stage
It is possible to configure the UCD7242 to supply 20A by tying the outputs of two power stages together. When
doing this it is required that the PWM pulse widths of the two PWM input signals be identical. The best way to do
this is to drive PWM-A and PWM-B from the same signal. This ensures that balanced volt seconds will be
applied to the external SW pins.
Copyright © 2013, Texas Instruments Incorporated
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