UCD7242-EP Datasheet, PDF (17/36 Pages) Texas Instruments – Digital Dual Synchronous-Buck Power Driver

UCD7242-EP
www.ti.com
SLVSBY2 – OCTOBER 2013
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
T_J - Junction Temperature - °C
Figure 15. Typical Characteristics
If the junction temperature exceeds approximately 170°C, the device will enter thermal shutdown. This will assert
the FLT pin, both MOSFETs will be turned off and the switch node will go high impedance. When the junction
temperature cools by approximately 20°C, the device will exit thermal shutdown and resume switching as
directed by the PWM and SRE pins. During a thermal shutdown event, the voltage on the Temp pin is driven to
3.3V.
FLT
This signal is a 3.3V digital output which is latched high when the current in the high-side FET exceeds the
current limit trip point. When tripped, high-side FET drive pulses are truncated to limit output current. FLT is
cleared on the falling edge of the first PWM pulse without a fault. Additionally, if the die temperature exceeds
170°C, the temperature sensor will initiate a thermal shutdown that halts output switching and sets the FLT flag.
Normal operation resumes when the die temperature falls below the thermal hysteresis band. The FLT flag will
clear after a PWM pulse occurs without a fault. Current limit is ignored during the high side blanking time. If an
over current event occurs during the blanking time the part will not initiate current limit for ~50ns.
PWM
ILIMIT
IL
HS
LS
FLT
Figure 16. FLT Signal
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