TPS54418A Datasheet, PDF (23/40 Pages) Texas Instruments – 2.95-V to 6-V Input, 4-A Output, 2-MHz , Synchronous Step-Down Switcher With Integrated FETs (SWIFT™)

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TPS54418A
SLVSC75A – AUGUST 2013 – REVISED SEPTEMBER 2016
9.2.2.4 Step Four: Select the Input Capacitor
The TPS54418A device requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least
4.7 μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes
any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage.
The capacitor must also have a ripple current rating greater than the maximum input current ripple of the device.
The input ripple current can be calculated using Equation 29.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor
decreases as the dc bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the
maximum input voltage. For this example, one 10 μF and one 0.1 μF 10 V capacitors in parallel have been
selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage
ripple can be calculated using Equation 30.
I_CIN(rms) = I_OUT ´
( ) _{VOUT ´} ^VIN₍min₎ ^{- V}OUT
V_IN(min)
V_IN(min)
(29)
DV_IN
=
I_OUT(max) ´ 0.25
C_IN ´ f_SW
(30)
Using the design example values, I_OUT(max) = 4 A, C_IN = 10 μF, f_SW = 1 MHz, yields an input voltage ripple of 99
mV and a rms input ripple current of 1.96 A.
9.2.2.5 Step Five: Minimum Load DC COMP Voltage
The TPS54418A implements a minimum COMP voltage clamp for improved load-transient response. The COMP
voltage tracks the peak inductor current, increasing as the peak inductor current increases, and decreases as the
peak inductor current decreases. During a severe load-dump event, for instance, the COMP voltage decreases
suddenly, falls below the minimum clamp value, then settles to a lower DC value as the control loop
compensates for the transient event. During the time when COMP reaches the minimum clamp voltage, turnon of
the high-side power switch is inhibited, keeping the low-side power switch on to discharge the output voltage
overshoot more quickly.
Proper application circuit design must ensure that the minimum load steady-state COMP voltage is above the +3
sigma minimum clamp to avoid unwanted inhibition of the high side power switch. For a given design, the steady-
state DC level of COMP must be measured at the minimum designed load and at the maximum designed input
voltage, then compared to the minimum COMP clamp voltage shown in Figure 22. These conditions give the
minimum COMP voltage for a given design. Generally, the COMP voltage and minimum clamp voltage move by
about the same amount with temperature. Increasing the minimum load COMP voltage is accomplished by
decreasing the output inductor value or the switching frequency used in a given design.
9.2.2.6 Step Six: Choose the Soft-Start Capacitor
The soft-start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
device reach the current limit or excessive current draw from the input power supply may cause the input voltage
rail to sag. Limiting the output voltage slew rate solves both of these problems.
The soft-start capacitor value can be calculated using Equation 31. For the example circuit, the soft-start time is
not too critical since the output capacitor value is 44 µF which does not require much current to charge to 1.8 V.
The example circuit has the soft-start time set to an arbitrary value of 4 ms which requires a 10 nF capacitor. In
the device, I_SS is 2 μA and V_REF is 0.8 V. For this application, maintain the soft-start time in the range between
1 ms and 10 ms.
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