TPS28225-Q1_15 Datasheet, PDF (23/38 Pages) Texas Instruments – TPS28225-Q1 High-Frequency 4-A Sink Synchronous MOSFET Drivers

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10 Layout
TPS28225-Q1
SLUSAR9B – DECEMBER 2011 – REVISED APRIL 2015
10.1 Layout Guidelines
To improve the switching characteristics and efficiency of a design, the following layout rules need to be followed.
• Locate the driver as close as possible to the MOSFETs.
• Locate the V_DD and bootstrap capacitors as close as possible to the driver.
• Pay special attention to the GND trace. Use the thermal pad of the DFN-8 package as the GND by
connecting it to the GND pin. The GND trace or pad from the driver goes directly to the source of the
MOSFET but should not include the high current path of the main current flowing through the drain and
source of the MOSFET.
• Use a similar rule for the PHASE node as for the GND.
• Use wide traces for UGATE and LGATE closely following the related PHASE and GND traces. Eighty to 100
mils width is preferable where possible.
• Use at least 2 or more vias if the MOSFET driving trace needs to be routed from one layer to another. For the
GND the number of vias are determined not only by the parasitic inductance but also by the requirements for
the thermal pad.
• Avoid PWM and enable traces going close to the PHASE node and pad where high dV/dT voltage can induce
significant noise into the relatively high impedance leads.
It should be taken into account that poor layout can cause 3% to 5% less efficiency versus a good layout design
and can even decrease the reliability of the whole system.
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