THMC50_08 Datasheet, PDF (23/34 Pages) Texas Instruments – REMOTE/LOCAL TEMPERATURE MONITOR AND FAN CONTROLLER WITH SMBus INTERFACE

THMC50
REMOTE/LOCAL TEMPERATURE MONITOR AND
FAN CONTROLLER WITH SMBus INTERFACE
SLIS090 – JULY 1999
PRINCIPLES OF OPERATION
reset generators timing diagrams (continued)
AUXRST
RST
t(RP)
t(RST)
VCC3AUX
AUXRST
RST
2.93V
t(RP)
t(VCC3AUX1)
t(VCC3AUX2)
t(RP)
TIME
Figure 19. AUXRST to RST Timing
TIME
Figure 20. VCC3AUX, AUXRST, and RST Timing
NAND tree tests - FAN_SPD/NTEST_IN and ADD/NTEST_OUT
A NAND tree is provided in the THMC50 for automated test equipment (ATE) board level connectivity testing.
If a logic 1 is applied to the FAN_SPD/NTEST_IN input terminal during initial power up, the device is in the NAND
tree test mode and the ADD/NTEST_OUT terminal becomes the NAND tree output. Power must be removed
from the device in order to return to normal operation. To perform a NAND tree test, MR, SDA, SCL, and GPI
terminals should be initially driven low, and FAN_SPD/NTEST_IN initially driven high. Starting with MR and
ending with GPI, each input should be toggled high and left high. This results in ADD/NTEST_OUT reflecting
the following pattern: (1 –> 0 –> 1 –> 0 –> 1) (see Figure 21).
FAN_SPD/NTEST_IN
AUXRST
D
Q
ENABLE
GPI
ENABLE
SCL
SDA
MR
Allow for a typical propagation delay of 500 ns.
GPI SCL SDA MR
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
1
1
1
1
ADD/NTEST_OUT
1
0
1
0
1
Figure 21. NAND Tree Test Equivalent Circuit
ADD/NTEST_OUT
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