SM320F28335-EP_16 Datasheet, PDF (23/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
Table 2-2. Signal Descriptions (continued)
NAME
XCLKOUT
XCLKIN
X1
X2
XRS
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
ADCLO
ADCRESEXT
ADCREFIN
ADCREFP
ADCREFM
V_DDA2
PIN NO.
PGF/P
TP
PIN #
GHH
BALL #
GJZ
BALL #
138 C11
A10
105 J14
G13
104 J13
G14
102 J11
H14
80
L10
M13
35
K4
K1
36
J5
K2
37
L1
L1
38
L2
L2
39
L3
L3
40
M1
M1
41
N1
M2
42
M3
M3
53
K5
N6
52
P4
M6
51
N4
N5
50
M4
M5
49
L4
N4
48
P3
M4
47
N3
N3
46
P2
P3
43
M2
N2
57
M5
P6
54
L5
P7
56
P5
P5
55
N5
P4
34
K2
K4
DESCRIPTION ⁽¹⁾
CLOCK
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half
the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 18:16
(XTIMCLK) and bit 2 (CLKMODE) in the XINTCNF2 register. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XINTCNF2[CLKOFF] to
1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during
a reset. (O/Z, 8 mA drive).
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this
case, the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.9-V
oscillator is used to feed clock to X1 pin), this pin must be tied to GND. (I)
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a
ceramic resonator may be connected across X1 and X2. The X1 pin is referenced to the
1.9-V core digital power supply. A 1.9-V external oscillator may be connected to the X1 pin.
In this case, the XCLKIN pin must be connected to ground. If a 3.3-V external oscillator is
used with the XCLKIN pin, X1 must be tied to GND. (I)
Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected
across X1 and X2. If X2 is not used it must be left unconnected. (O)
RESET
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the
address contained at the location 0x3FFFC0. When XRS is brought to a high level,
execution begins at the location pointed to by the PC. This pin is driven low by the DSC
when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the
watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑)
The output buffer of this pin is an open-drain with an internal pullup. It is recommended
that this pin be driven by an open-drain device.
ADC SIGNALS
ADC Group A, Channel 7 input (I)
ADC Group A, Channel 6 input (I)
ADC Group A, Channel 5 input (I)
ADC Group A, Channel 4 input (I)
ADC Group A, Channel 3 input (I)
ADC Group A, Channel 2 input (I)
ADC Group A, Channel 1 input (I)
ADC Group A, Channel 0 input (I)
ADC Group B, Channel 7 input (I)
ADC Group B, Channel 6 input (I)
ADC Group B, Channel 5 input (I)
ADC Group B, Channel 4 input (I)
ADC Group B, Channel 3 input (I)
ADC Group B, Channel 2 input (I)
ADC Group B, Channel 1 input (I)
ADC Group B, Channel 0 input (I)
Low Reference (connect to analog ground) (I)
ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
External reference input (I)
Internal Reference Positive Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass
capacitor of 2.2 μF to analog ground. (O)
Internal Reference Medium Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass
capacitor of 2.2 μF to analog ground. (O)
CPU AND I/O POWER PINS
ADC Analog Power Pin
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