SM320F28335-EP_16 Datasheet, PDF (130/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
SPISOMI
SPISIMO
12
13
14
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17
18
SPISOMI Data Is Valid
21
22
SPISIMO Data
Must Be Valid
Data Valid
SPISTE^(A)
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5t_c(SPC) before the valid SPI clock edge and
remain low for at least 0.5t_c(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-22. SPI Slave Mode External Timing (Clock Phase = 1)
6.14 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the
Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF
zone. Table 6-35 shows the relationship between the parameters configured in the XTIMING register and
the duration of the pulse in terms of XTIMCLK cycles.
Table 6-35. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DESCRIPTION
DURATION (ns)^{(1) (2)}
X2TIMING = 0
X2TIMING = 1
LR
Lead period, read access
AR
Active period, read access
TR
Trail period, read access
LW
Lead period, write access
AW
Active period, write access
TW
Trail period, write access
XRDLEAD × t_c(XTIM)
(XRDACTIVE + WS + 1) × t_c(XTIM)
XRDTRAIL × t_c(XTIM)
XWRLEAD × t_c(XTIM)
(XWRACTIVE + WS + 1) × t_c(XTIM)
XWRTRAIL × t_c(XTIM)
(XRDLEAD × 2) × t_c(XTIM)
(XRDACTIVE × 2 + WS + 1) × t_c(XTIM)
(XRDTRAIL × 2) × t_c(XTIM)
(XWRLEAD × 2) × t_c(XTIM)
(XWRACTIVE × 2 + WS + 1) × t_c(XTIM)
(XWRTRAIL × 2) × t_c(XTIM)
(1) t_c(XTIM) − Cycle time, XTIMCLK
(2) WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No
internal device hardware is included to detect illegal settings.
6.14.1 USEREADY = 0
If the XREADY signal is ignored (USEREADY = 0), then:
130 Electrical Specifications
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