OPA354A-Q1 Datasheet, PDF (23/37 Pages) Texas Instruments – 250-MHz, Rail-to-Rail I/O, CMOS Operational Amplifiers

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OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
SBOS492E – JUNE 2009 – REVISED AUGUST 2016
9.1 Power Dissipation
Power dissipation depends on power-supply voltage, signal and load conditions. With dc signals, power
dissipation is equal to the product of output current times the voltage across the conducting output transistor,
V_S – V_O. Minimize power dissipation by using the lowest possible power-supply voltage necessary to assure the
required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a dc output voltage of one-half the power-supply
voltage. Dissipation with ac signals is lower. Application bulletin AB-039, Power Amplifier Stress and Power
Handling Limitations explains how to calculate or measure power dissipation with unusual signals and loads, and
can be found at www.ti.com.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, limit junction temperature to 150°C, maximum. To estimate the margin of safety
in a complete design, increase the ambient temperature to trigger the thermal protection at 160°C. The thermal
protection should trigger more than 35°C above the maximum expected ambient condition of the application.
10 Layout
10.1 Layout Guidelines
Use good high-frequency printed circuit board (PCB) layout techniques for the OPAx354-Q1 family of devices.
Generous use of ground planes, short and direct signal traces, and a suitable bypass capacitor located at the V+
pin assure clean stable operation. Large areas of copper also provides a means of dissipating heat that is
generated in normal operation. Sockets are not recommended for use with any high-speed amplifier. A 10-nF
ceramic bypass capacitor is the minimum recommended value; adding a 1-μF or larger tantalum capacitor in
parallel can be beneficial when driving a low-resistance load. Providing adequate bypass capacitance is essential
to achieving very low harmonic and intermodulation distortion.
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-
impedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to
physically separate digital and analog grounds, paying attention to the flow of the ground current. For
more detailed information, refer to Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the
inverting input minimizes parasitic capacitance, as shown in Figure 44.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
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