BQ2023_16 Datasheet, PDF (23/32 Pages) Texas Instruments – SINGLE-WIRE ADVANCED BATTERY MONITOR IC

Not Recommended for New Designs
bq2023
SINGLEĆWIRE ADVANCED BATTERY MONITOR IC
FOR CELLULAR AND PDA APPLICATIONS
SLUS480B – MAY 2001
APPLICATION INFORMATION
register descriptions (continued)
flash erase disable (FED) register
The FED register (address 101 hex) contains the bits that disable the flash erase on page boundaries. When
a bit is cleared, the corresponding page of flash can no longer be programmed or erased. Once a disable erase
page bit has been set, it cannot be cleared. This register is a flash register, programmed using the write memory
command protocol, and it requires issuing the program code 5A hex after CRC verification.
7
RSVD
6
PAGE6
5
PAGE5
FED BITS
4
3
PAGE4 PAGE3
2
PAGE2
1
PAGE1
0
PAGE0
RSVD Reserved for future use.
PAGE6 The PAGE6 bit disables PROGRAM/ERASE for flash memory locations C0 through DF hex when
set to 0.
PAGE5 The PAGE5 bit disables PROGRAM/ERASE for flash memory locations A0 through BF hex when
set to 0.
PAGE4 The PAGE4 bit disables PROGRAM/ERASE for flash memory locations 80 through 9F hex when set
to 0.
PAGE3 The PAGE3 bit disables PROGRAM/ERASE for flash memory locations 60 through 7F hex when set
to 0.
PAGE2 The PAGE2 bit disables PROGRAM/ERASE for flash memory locations 40 through 5F hex when set
to 0.
PAGE1 The PAGE1 bit disables PROGRAM/ERASE for flash memory locations 20 through 3F hex when set
to 0.
PAGE0 The PAGE0 bit disables PROGRAM/ERASE for flash memory locations 00 through 1F hex when set
to 0.
CRC generation
The bq2023 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute
a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the bq2023 to
determine if the ROM data have been received error-free by the bus master. The equivalent polynomial function
of this CRC is: X⁸ + X⁵ + X⁴ +1. The CRC generator circuit is shown in Figure 14.
Under certain conditions, the bq2023 also generates an 8-bit CRC value using the same polynomial function
shown above and provides this value to the bus master to validate the transfer of command, address, and data
bytes from the bus master to the bq2023. The bq2023 receives data bytes for the write memory and flash page
erase commands. It computes an 8-bit CRC for the command, address, and data bytes of each of these
commands and then outputs this value to the bus master to confirm proper transfer. Similarly the bq2023
computes an 8-bit CRC for the command and address bytes received from the bus master for the Read Memory
commands to confirm that these bytes have been received correctly.
In each case where a CRC is used for data transfer validation, the bus master must calculate a CRC value using
the polynomial function given above and compare the calculated value to either the 8-bit CRC value stored in
the 64-bit ROM portion of the bq2023 (for ROM reads) or the 8-bit CRC value computed within the bq2023. The
comparison of CRC values and decision to continue with an operation are determined entirely by the bus master.
There is no circuitry on the bq2023 that prevents a command sequence from proceeding if the CRC stored in
or calculated by the bq2023 does not match the value generated by the bus master.
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