ADS7044 Datasheet, PDF (23/37 Pages) Texas Instruments – Ultra-Low Power, Ultra-Small Size, 12-Bit, 1-MSPS, SAR ADC

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ADS7044
SBAS682A – NOVEMBER 2014 – REVISED NOVEMBER 2014
Typical Applications (continued)
9.2.1.2.1 Antialiasing Filter
Converting analog-to-digital signals requires sampling an input signal at a rate greater than or equal to the
Nyquist rate. Any higher frequency content in the input signal beyond half the sampling frequency is digitized and
folded back into the low-frequency spectrum. This process is called aliasing. Therefore, an external, antialiasing
filter must be used to remove the harmonic content from the input signal before being sampled by the ADC. An
antialiasing filter is designed as a low-pass RC filter, for which the 3-dB bandwidth is optimized for noise,
response time, and throughput. For dc signals with fast transients (including multiplexed input signals), a high-
bandwidth filter is designed to allow the signal to be accurately set at the ADC inputs during the small acquisition
time window. Figure 40 provides the equation for determining the bandwidth of antialiasing filter.
AVDD
f _3dB 
1
2ΠK 2R_FLT K C_FLT
R_FLT
R_FLT
C_FLT
AINP
AVDD
Device
AINM
GND
Figure 40. Antialiasing Filter
For ac signals, the filter bandwidth must be kept low to band limit the noise fed into the ADC input, thereby
increasing the signal-to-noise ratio (SNR) of the system. Besides filtering the noise from the front-end drive
circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage
of the ADC. A filter capacitor, C_FLT, is connected across the ADC inputs. This capacitor helps reduce the
sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold
capacitors during the acquisition process. As a rule of thumb, the value of this capacitor must be at least 20
times the specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is
equal to 15 pF. Thus, the value of C_FLT must be greater than 300 pF. The capacitor must be a COG- or NPO-
type because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical
characteristics under varying voltages, frequency, and time.
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (R_FLT) are used at the output of
the amplifiers. A higher value of R_FLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of R_FLT requires balancing the stability
and distortion of the design.
The input amplifier bandwidth must be much higher than the cutoff frequency of the antialiasing filter. TI strongly
recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase margin with
the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers may
require more bandwidth than others to drive similar filters.
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