ADS7044 Datasheet, PDF (20/37 Pages) Texas Instruments – Ultra-Low Power, Ultra-Small Size, 12-Bit, 1-MSPS, SAR ADC

ADS7044
SBAS682A – NOVEMBER 2014 – REVISED NOVEMBER 2014
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Device Functional Modes (continued)
8.4.1.1 Offset Calibration on Power-Up
The device starts offset calibration on the first CS falling edge after power-up and calibration completes if the CS
pin remains low for at least 16 SCLKs after the first CS falling edge. The SDO output remains low during
calibration. The minimum acquisition time must be provided after calibration for acquiring the first sample. If the
device is not provided with at least 16 SCLKs during the first serial transfer frame after power-up, the OCR is not
updated. Table 2 provides the timing parameters for offset calibration on power-up.
For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The
conversion result adjusted with the value stored in OCR is provided by the device on the SDO output. Figure 37
illustrates the timing diagram for offset calibration on power-up.
Table 2. Offset Calibration on Power-Up
f_CLK-CAL
f_CLK-CAL
t_POWERUP-CAL
t_ACQ
t_{PH_CS}
PARAMETER
SCLK frequency for calibration at 2.25 V < AVDD < 3.6 V
SCLK frequency for calibration at 1.8 V < AVDD < 2.25 V
Calibration time at power-up
Acquisition time
CS high time
MIN
16 t_SCLK
200
t_ACQ
TYP
MAX
16
12
UNIT
MHz
MHz
ns
ns
ns
Start
Power-up
Calibration
t_POWERUP-CAL
t_{PH_CS}
t_ACQ
Sample
#1
CS
t_{SU_CSCK}
t_{D_CKCS}
SCLK(f_CLK-CAL)
1
2
15 16
SDO
Figure 37. Offset Calibration on Power-Up Timing Diagram
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