TPS24710_15 Datasheet, PDF (22/38 Pages) Texas Instruments – High-Efficiency Power-Limiting Hot-Swap Controller

TPS24710, TPS24711
TPS24712, TPS24713
SLVSAL2G – JANUARY 2011 – REVISED NOVEMBER 2015
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Device Functional Modes (continued)
1. In the inrush mode, TIMER begins to source current to the timer capacitor, C_T, when MOSFET M₁ is
enabled. TIMER begins to sink current from the timer capacitor, C_T when V_{(GATE – VCC)} exceeds the timer
activation voltage (see the Inrush Operation section). If V_{(GATE – VCC)} does not reach the timer activation
voltage before TIMER reaches 1.35 V, then the TPS24710/11/12/13 disables the external MOSFET M₁. After
the MOSFET turns off, the timer goes into either latch mode (TPS24710/12) or retry mode (TPS24711/13).
2. In an overload fault, TIMER begins to source current to the timer capacitor, C_T, when the load current
exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of
1.35 V, TIMER begins to sink current from the timer capacitor, C_T, and the GATE pin is pulled to ground.
After the fault timer period, TIMER may go into latch mode (TPS24710/12) or retry mode (TPS24711/13).
3. In output short-circuit fault, TIMER begins to source current to the timer capacitor, C_T, when the load current
exceeds the programmed current limits following a fast-trip shutdown of M₁. When the timer capacitor voltage
reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, C_T, and the
GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24710/12) or
retry mode (TPS24711/13).
If the fault current drops below the programmed current limit within the fault timer period, V_TIMER decreases and
the pass MOSFET remains enabled.
The behaviors of TIMER are different in the latch mode (TPS24710/12) and retry mode (TPS24711/13). If the
timer capacitor reaches the upper threshold of 1.35 V, then:
• In latch mode, the GATE remains low and the TIMER pin continues to charge and discharge the attached
capacitor periodically until TPS24710/12 is disabled by UVLO or EN as shown in Figure 34.
• In retry mode, TIMER charges and discharges C_T between the lower threshold of 0.35 V and the upper
threshold of 1.35 V for sixteen cycles before the TPS24711/13 attempts to re-start. The TIMER pin is pulled
to GND at the end of the 16^th cycle of charging and discharging and then ramps from 0 V to 1.35 V for the
initial half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload
fault is removed or the TPS24711/13 is disabled by UVLO or EN.
8.4.7 Overtemperature Shutdown
The TPS24710/11/12/13 includes a built-in overtemperature shutdown circuit designed to disable the gate driver
if the die temperature exceeds approximately 140°C. An overtemperature condition also causes the FLT, PG,
FLTb and PGb pins to go to high-impedance states. Normal operation resumes once the die temperature has
fallen approximately 10°C.
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