OPA1612-Q1 Datasheet, PDF (22/31 Pages) Texas Instruments – SoundPlus High-Performance, Bipolar-Input Audio Operational Amplifier

OPA1612-Q1
SLOS931A – NOVEMBER 2015 – REVISED NOVEMBER 2015
Typical Application (continued)
9.2.3 Application Curves
Equation 1 applies to Figure 40 and Figure 41.
10k
Total Output Voltage Noise
Resistor Noise
1k
100
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E_O
R_S
10
1
100
1k
10k
100k
1M
Source Resistance, R_S (Ω)
Figure 40. Noise Performance of the OPA1612-Q1
in Unity-Gain Buffer Configuration
Figure 41. Circuit for Figure 40
10 Power-Supply Recommendations
The OPA1612-Q1 device is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications
apply from –40°C to +85°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds while paying attention to the flow of the ground current. For more detailed information,
refer to the application report, Circuit Board Layout Techniques (SLOA089).
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be keep them separate, crossing the sensitive trace perpendicular as
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