LMX2581_16 Datasheet, PDF (22/56 Pages) Texas Instruments – LMX2581 Wideband Frequency Synthesizer with Integrated VCO

LMX2581
SNAS601G – AUGUST 2012 – REVISED SEPTEMBER 2014
PARAMETER
Charge Pump Gain in Fastlock
Loop Bandwidth Multiplier
External Resistor
Table 9. Fastlock Configuration
SYMBOL
FL_CPG
K
R2pLF
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CALCULATION
Typically use the highest value.
K=sqrt(FL_CPG/CPG)
R2 / (K-1)
8.3.13 Lock Detect
The LMX2581 offers two circuits to detect lock, Vtune and Digital Lock Detect, which may be used separately or
in conjunction. Digital Lock Detect gives a reliable indication of lock/unlock if programmed correctly with the one
exception, which occurs when the PLL is locked to a valid OSCin signal and then the OSCin signal is abruptly
removed. In this case, digital lock detect can sometimes still indicate a locked state, but Vtune Lock detect will
correctly indicate an unlocked state. Therefore, for the most reliable lock detect, it is recommended to use these
in conjunction, because each technique's drawback is covered by the other one. Note that because the
powerdown mode powers down the lock detect circuitry, it is possible to get a high lock detect indication when
the device is powered down. The details of the two respective methods are described below in the Vtune Lock
Detect and Digital Lock Detect (DLD) sections.
8.3.13.1 Vtune Lock Detect
This style of lock detect only works with the internal VCO. Whenever the tuning voltage goes below the threshold
of about 0.5 V, or above the threshold of about 2.2 V, the internal VCO will become unlocked and the Vtune lock
detect will indicate that the device is unlocked. For this reason, when the Vtune lock detect says the PLL is
unlocked, one can be certain that it is unlocked.
8.3.13.2 Digital Lock Detect (DLD)
This lock detect works by comparing the phase error as presented to the phase detector. If the phase error plus
the delay as specified by the PFD_DLY word outside the tolerance as specified by DLD_TOL, then this
comparison would be considered to be an error, otherwise passing. At higher phase detector frequencies, it may
be necessary to adjust the DLD_ERR_CNT and DLD_PASS_CNT. The DLD_ERR_CNT specifies how may
errors are necessary to cause the circuit to consider the PLL to be unlocked. The DLD_PASS_CNT multiplied by
8 specifies how many passing comparisons are necessary to cause the PLL to be considered to be locked and
also resets the count for the errors. The DLD_ERR_CNT and DLD_PASS_CNT values may be decreased to
make the circuit more sensitive, but if lock detect is made too sensitive, chattering can occur and these values
should be increased.
8.3.14 Part ID and Register Readback
8.3.14.1 Uses of Readback
The LMX2581 allows any of its registers to be read back, which could be useful for the following applications
below.
• Register Readback
– By reading back the register values, it can be confirmed that the correct information was written. In
addition to this, Register R6 has special diagnostic information that could potentially be useful for
debugging problems.
• Part ID Readback
– By reading back the part ID, this information may be used by whatever device is programming the
LMX2581 to identify this device and know what programming information to send. In addition to this, the
BUFEN and CE pins may be used to create 4 unique part ID values. Although these pins can impact the
device, they may be overridden in software. It is not necessary to have the device programmed in order to
do part ID Readback.
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