LMX2581_16 Datasheet, PDF (14/56 Pages) Texas Instruments – LMX2581 Wideband Frequency Synthesizer with Integrated VCO

LMX2581
SNAS601G – AUGUST 2012 – REVISED SEPTEMBER 2014
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Feature Description (continued)
8.3.2 Impact of Temperature on VCO Phase Noise
The phase noise specifications for the VCO in Electrical Characteristics are for a narrow loop bandwidth at room
temperature. If the temperature is changed, Table 1 gives an approximation on how the VCO phase noise is
impacted. For instance, if one was to lock the PLL at -40°C and then measure the phase noise at 1 MHz offset,
the phase noise would typically be of the order of 2 dB better than if it was locked and measured at 25°C. If the
PLL is locked at -40°C and then the temperature was to drift to 85°C, then the phase noise at 1 MHz offset would
typically be about 2 dB worse than it would be if it was locked and measured at 25°C. These numbers are only
approximations and may change between devices and over VCO cores slightly.
Table 1. Approximate Change in VCO Phase Noise vs. Temperature and Temperature Drift in dB
STARTING
TEMPERATURE
-40°C
25°C
85°C
FINAL
TEMPERATURE
-40°C
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
OFFSET
10 kHz
100 kHz
1 MHz
10 MHz
40 MHz
-2
-1
-2
-2
0
-1
0
0
-1
0
-3
2
2
-0
0
-1
-1
0
-1
0
These are all zero because all measurements are relative to this row.
-3
2
2
0
0
-4
-2
-2
0
0
-1
0
0
-2
0
-2
2
2
0
0
8.3.3 OSCin INPUT and OSCin Doubler
The OSCin pin is driven with a single-ended signal which is used as a frequency reference. Before the OSCin
frequency reaches the phase detector, it may be doubled with the OSCin doubler and/or divided with the PLL R
divider.
Because the OSCin signal is used as a clock for the VCO calibration, the OSC_FREQ word needs to be
programmed correctly and a proper signal needs to be applied at the OSCin pin at the time of programming the
R0 register in order for the VCO calibration to properly work. Higher slew rates tend to yield the best fractional
spurs and phase noise, so a square wave signal is best for OSCin. If using a sine wave, higher frequencies tend
to yield better phase noise and fractional spurs due to their higher slew rates. The OSCin pin has high
impedance, so for optimal performance, it is recommended to use either a shunt resistor or resistive pad to make
sure that the impedances looking towards and away from the device input are both close to 50 Ω.
8.3.4 R Divider
The R divider divides the OSCin frequency down to the phase detector frequency. With this device, it is possible
to use both the doubler and the R divider at the same time.
8.3.5 PLL N Divider And Fractional Circuitry
The N divider includes fractional compensation and can achieve any fractional denominator (PLL_DEN) from 1 to
4,194,303. The integer portion, PLL_N, is the whole part of the N divider value and the fractional portion,
PLL_NUM / PLL_DEN, is the remaining fraction. PLL_N, PLL_NUM, and PLL_DEN are software programmable.
So in general, the total N divider value, N, is determined by: N = PLL_N + PLL_NUM / PLL_DEN. The order of
the delta sigma modulator is programmable from integer mode to third order. There are also several dithering
modes that are also programmable. In order to make the fractional spurs consistent, the modulator is reset any
time that the R0 register is programmed.
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