DS90UB913Q-Q1 Datasheet, PDF (22/70 Pages) Texas Instruments – 10- to 100-MHz, 10- and 12-Bit DC-Balanced FPD-Link III Serializer and Deserializer With Bidirectional Control Channel

DS90UB913Q-Q1, DS90UB914Q-Q1
SNLS420D – JULY 2012 – REVISED JULY 2015
AC Timing Diagrams and Test Circuits (continued)
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D_IN
SYMBOL N
SYMBOL N+1
PCLK
VDDIO/2
SYMBOL N+2
t_SD
SYMBOL N+3
DOUT+-
SYMBOL N-4
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
0V
Figure 15. Serializer Delay
RIN± 0V
PCLK
ROUTn
PDB ^VDDIO/2
R_IN±
t_DDLT
LOCK TRI-STATE
VDDIO/2
Figure 16. Deserializer Data Lock Time
Deserializer
8 pF
lumped
80%
20%
t_CLH
80%
20%
t_CHL
Figure 17. Deserializer LVCMOS Output Load and Transition Times
SYMBOL N
SYMBOL N + 1
SYMBOL N + 2
SYMBOL N + 3
SYMBOL N + 3
SYMBOL N - 3
t_DD
SYMBOL N - 2
VDDIO/2
SYMBOL N - 1
SYMBOL N
SYMBOL N+1
Figure 18. Deserializer Delay
PCLK
ROUT[n],
VS, HS
t_RCP
1/2 V_DDIO
1/2 V_DDIO
1/2 V_DDIO
t_ROS
t_ROH
1/2 V_DDIO
V_DDIO
0V
V_DDIO
0V
Figure 19. Deserializer Output Set-Up and Hold Times
22
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