ADC121S655 Datasheet, PDF (22/31 Pages) National Semiconductor (TI) – 12-Bit, 200 kSPS to 500 kSPS, Differential Input, Micro Power A/D Converter

ADC121S655
SNAS402A – MAY 2007 – REVISED MARCH 2013
www.ti.com
TIMING CONSIDERATIONS
Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS
occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is
clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature,
and characteristics of the individual device. To ensure that the data is always clocked out at a given time (the 5th
falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in the
Timing Specification table.
PCB LAYOUT AND CIRCUIT CONSIDERATIONS
For best performance, care should be taken with the physical layout of the printed circuit board. This is especially
true with a low reference voltage or when the conversion rate is high. At high clock rates there is less time for
settling, so it is important that any noise settles out before the conversion begins.
Power Supply
Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may
originate from switching power supplies, digital logic, high power devices, and other sources. Power to the
ADC121S655 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor and a 1 µF to 10 µF
capacitor should be used to bypass the ADC121S655 supply, with the 0.1 µF capacitor placed as close to the
ADC121S655 package as possible.
Voltage Reference
The reference source must have a low output impedance and needs to be bypassed with a minimum capacitor
value of 0.1 µF. A larger capacitor value of 1 µF to 10 µF placed in parallel with the 0.1 µF is preferred. While the
ADC121S655 draws very little current from the reference on average, there are higher instantaneous current
spikes at the reference input that must settle out while SCLK is high. Since these transient spikes can be as high
as 20 mA, it is important that the reference circuit be capable of providing this much current and settle out during
the first three clock periods (acquisition time).
The reference input of the ADC121S655, like all A/D converters, does not reject noise or voltage variations. Keep
this in mind if the reference voltage is derived from the power supply. Any noise and/or ripple from the supply
that is not rejected by the external reference circuitry will appear in the digital results. The use of an active
reference source is recommended. The LM4040 and LM4050 shunt reference families and the LM4132 and
LM4140 series reference families are excellent choices for a reference source.
Power and Ground Planes
A single ground plane and the use of two or more power planes is recommended. The power planes should all
be in the same board layer and will define the analog, digital, and high power board areas. Lines associated with
these areas should always be routed within their respective areas.
The GND pin on the ADC121S655 should be connected to the ground plane at a quiet point. Avoid connecting
the GND pin too close to the ground point of a microprocessor, microcontroller, digital signal processor, or other
high power digital device.
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