LM3S5T36 Datasheet, PDF (215/1050 Pages) Texas Instruments – Stellaris® LM3S5T36 Microcontroller

Stellaris^® LM3S5T36 Microcontroller
Bit/Field
22
21
20
19:17
16:14
13
Name
USESYSDIV
reserved
USEPWMDIV
PWMDIV
reserved
PWRDN
Type
R/W
RO
R/W
R/W
RO
R/W
Reset
0
Description
Enable System Clock Divider
Value Description
1 The system clock divider is the source for the system clock. The
system clock divider is forced to be used when the PLL is
selected as the source.
If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2
field in the RCC2 register is used as the system clock divider
rather than the SYSDIV field in this register.
0 The system clock is used undivided.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Enable PWM Clock Divisor
Value Description
1 The PWM clock divider is the source for the PWM clock.
0 The system clock is the source for the PWM clock.
Note that when the PWM divisor is used, it is applied to the clock for
both PWM modules.
0x7
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. The rising
edge of this clock is synchronous with the system clock.
Value Divisor
0x0 /2
0x1 /4
0x2 /8
0x3 /16
0x4 /32
0x5 /64
0x6 /64
0x7 /64 (default)
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
PLL Power Down
Value Description
1 The PLL is powered down. Care must be taken to ensure that
another clock source is functioning and that the BYPASS bit is
set before setting this bit.
0 The PLL is operating normally.
January 21, 2012
215
Texas Instruments-Production Data