TM4C1231E6PM_15 Datasheet, PDF (211/1145 Pages) Texas Instruments – Tiva™ TM4C1231E6PM Microcontroller

Tiva^™ TM4C1231E6PM Microcontroller
■ Crystal input selection
Important: Write the RCC register prior to writing the RCC2 register.
When transitioning the system clock configuration to use the MOSC as the fundamental
clock source, the MOSCDIS bit must be set prior to reselecting the MOSC or an undefined
system clock configuration can sporadically occur.
The configuration of the system clock must not be changed while an EEPROM operation
is in process. Software must wait until the WORKING bit in the EEPROM Done Status
(EEDONE) register is clear before making any changes to the system clock.
Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system
clock signal and can be individually enabled/disabled. The ADC clock signal can be selected from
the PIOSC, the system clock if the PLL is disabled, or the PLL output divided down to 16 MHz if the
PLL is enabled.
Note: If the ADC module is not using the PIOSC as the clock source, the system clock must be
at least 16 MHz.
Figure 5-5. Main Clock Tree
XTAL^a
PWRDN ^b
MOSCDIS ^a
Main OSC
PLL
(400 MHz)
IOSCDIS^a
Precision
Internal OSC
(16 MHz)
Internal OSC
(30 kHz)
Hibernation
OSC
(32.768 kHz)
÷4
OSCSRC ^b,d
DIV400 ^c
÷2
BYPASS ^b,d
USESYSDIV ^a,d
÷ SYSDIV^e
BYPASS ^b,d
PWRDN
÷ 25
CS ^f
UART Baud Clock
System Clock
CS ^f
SSI Baud Clock
CS ^f
ADC Clock
Note:
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit
USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
e. Control provided by RCC register SYSDIV field, RCC2 register SYSDIV2 field if overridden with USERCC2
bit, or [SYSDIV2,SYSDIV2LSB] if both USERCC2 and DIV400 bits are set.
f. Control provided by UARTCC, SSICC, and ADCCC register field.
June 12, 2014
211
Texas Instruments-Production Data