TPS2373 Datasheet, PDF (21/42 Pages) Texas Instruments – High-Power PoE PD Interface with Advanced Startup

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TPS2373
SLUSCD1 – APRIL 2017
7.4.6 Inrush and Startup
IEEE 802.3bt has a startup current and time limitation, providing compatibility between a PSE of any Type and a
PD of any Type. The PSE inrush limit varies according to the allotted power. If Class 0 to 4, Class 5 to 6 or Class
7 to 8, the inrush limit is respectively from 400 mA to 450 mA, 400 mA to 900 mA or 800 mA to 900 mA. PSE
inrush limit applies for up to 75 ms after power up (applying "48 V" to the PI), after which the Type 2, 3, or 4 PSE
will support a higher output current in accordance with the allocated class. The TPS2373-3 and TPS2373-4
respectively implement a 200-mA and 335-mA inrush current, which is compatible with all PSE Types. A high-
power PD must limit its converter startup peak current. The operational current for Type 2 and 3, and preferably
Type 4, cannot exceed 400 mA for a period of 80 ms.
7.4.7 Maintain Power Signature
The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating
voltage is applied. For a Type 1 or Type 2 PD, a valid MPS consists of a minimum dc current of 10 mA, or a 10-
mA pulsed current for at least 75 ms every 325 ms, and an AC impedance lower than 26.3 kΩ in parallel with
0.05 μF. Only Type 1 and Type 2 PSEs monitor the AC MPS. A Type 1 or Type 2 PSE that monitors only the AC
MPS may remove power from the PD.
To enable applications with stringent standby requirements, IEEE802.3bt introduced a significant change
regarding the minimum pulsed current duration to assure the PSE will maintain power. This applies to all Type 3
and Type 4 PSEs, and the pulse duration is ~10% of what is required for Type 1 and 2 PSEs. The MPS current
amplitude requirement for Class 5-8 PDs have also increased to 16 mA at the PSE end of the ethernet cable.
If the current through the RTN-to-VSS path is below ~26.5 mA, the TPS2373 automatically generates the MPS
pulsed current through the AMPS_CTL output pin, the current amplitude being adjustable with an external
resistor. The TPS2373 is also able to determine if the PSE is of Type 1-2 or Type 3-4, automatically adjusting the
MPS pulse duration and duty-cycle. Note that the IEEE802.3bt requirement for the PD is applicable at the PSE
end of the cable. That means that depending the cable length and other parameters including the bulk
capacitance, a longer MPS duration may be required to ensure a valid MPS. For that purpose, the TPS2373 has
3 different selections of MPS pulse duration and duty-cycle, selectable through the MPS_DUTY input pin. Note
that the MPS pulsed mode also applies when APD is pulled high.
When DEN is used to force the hotswap switch off, the DC MPS will not be met. A PSE that monitors the DC
MPS will remove power from the PD when this occurs.
7.4.8 Advanced Startup and Converter Operation
The internal PoE UVLO (Undervoltage Lock Out) circuit holds the hotswap switch off before the PSE provides full
voltage to the PD. This prevents the downstream converter circuits from loading the PoE input during detection
and classification. The converter circuits will discharge C_BULK while the PD is unpowered. Thus V_(VDD-RTN) will be
a small voltage just after full voltage is applied to the PD, as seen in Figure 4. The PSE drives the PI voltage to
the operating range once it has decided to power up the PD. When V_VDD rises above the UVLO turn-on threshold
(V_{UVLO_R}, approximately 38 V) with RTN high, the TPS2373-3 and TPS2373-4 enables the hotswap MOSFET
with inrush current limit (~200 mA for TPS2373-3 and ~335 mA for TPS2373-4) as seen in Figure 6. The PG pin
is in low state while C_BULK charges and V_RTN falls from V_VDD to nearly V_VSS. VC_OUT output is also turned off
during that time, providing no low supply voltage to the PWM controller, to avoid additional loading between V_VDD
and V_RTN that could prevent successful PD and subsequent converter start up. Once the inrush current falls
about 10% below the inrush current limit, the PD current limit switches to the operational level (~1.8 A for
TPS2373-3 and ~2.2 A for TPS2373-4).
Additionally, as seen in Figure 7 once the inrush period duration has also exceeded ~81.5 ms, PG output
becomes high impedance and the PWM controller startup source is turned on charging C_{VC_OUT}, the VC_OUT
capacitor, and allowing the downstream converter circuitry to start. As seen in Figure 7, the converter soft-start
introduces a slight additional delay before the start of switching. Note that the startup source current capability is
such that it can fully maintain V_{VC_OUT} during the converter soft-start without requiring any significant C_{VC_OUT}
capacitance. Once V_{VC_IN} has risen above V_{VCIN_ON} (~8.5 V), meaning that the DC-DC converter has ramped up
its output voltage, VC_IN pin is internally connected to VC_OUT pin. The startup current source is then turned off
~24 ms (t_TPLHBT) later, completing the startup. TPH, TPL and BT outputs are enabled within t_TPLHBT following
V_{VC_IN} rising above V_{VCIN_ON}. If there is a fault condition preventing V_{VC_IN} from rising during converter startup (for
example a short-circuit at the output of the downstream converter), a t_{STUP_OUT} (~50 ms) timeout period is applied
at the end of which the startup source is turned off and the VC switch is turned on, until V_{VC_OUT} falls below
V_{VCO_UV} to initiate a new startup cycle.
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