TPS2373 Datasheet, PDF (13/42 Pages) Texas Instruments – High-Power PoE PD Interface with Advanced Startup

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TPS2373
SLUSCD1 – APRIL 2017
thermal shutdown, if VC_OUT voltage falls below its UVLO threshold, or if VDD-to-VSS voltage falls below ~32
V. Note that in all these cases, as long as VDD-to-VSS voltage remains above the mark reset threshold, the
internal logic state of these 3 signals is remembered such that these outputs will be activated accordingly after
the startup has completed. This circuit resets when the VDD-to-VSS voltage drops below the mark reset
threshold. The TPH, TPL and BT pins can be left unconnected if not used.
PSE Type
1-2
1-2
1-2
1-2
2
3-4
3-4
3-4
3-4
3-4
3-4
3-4
4
4
Table 2. TPH, TPL, BT and Allocated Power Truth Table
PD Class
0
1
2
3
4
0
1
2
3
4
5
6
7
8
NUMBER OF
CLASS CYCLES
1
1
1
1
2
1
1
1
1
2-3
4
4
5
5
PSE
ALLOCATED
POWER AT PD
(W)
12.95
3.84
6.49
12.95
25.5
12.95
3.84
6.49
12.95
25.5
40
51
62
71
TPH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
TPL
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
HIGH
LOW
LOW
BT
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
PSE Type
3-4
3-4
3-4
PD Class
4-8
5-8
7-8
Table 3. Power Demotion Cases
NUMBER OF
CLASS CYCLES
1
2,3
4
PSE
ALLOCATED
POWER AT PD
(W)
12.95
25.5
51
TPH
HIGH
HIGH
LOW
TPL
HIGH
LOW
HIGH
BT
LOW
LOW
LOW
7.3.7 VC_IN, VC_OUT, UVLO_SEL and Advanced PWM Startup
VC_OUT provides the auxiliary power supply for the external DC-DC controller. After the inrush phase has
completed, VC_OUT initially sources the startup current from VDD input, then it is internally connected to VC_IN
once V_{VC_IN} has exceeded approximately 8.5 V, meaning that the DC-DC converter has ramped up its output
voltage, or if V_{VC_IN} has remained below 8.5 V for more than about 50 ms (time out period). VC_IN is usually fed
by a bias winding of the DC-DC converter's power transformer to sustain operation after startup. The startup
current source is turned on at the end of the inrush phase, and it is turned off about 24 ms after the VC switch,
connecting VC_IN and VC_OUT together, has been turned on. Due to the high current capability of the startup
source, the recommended capacitance at VC_OUT is relatively small, typically 1 µF in most applications,
including when there is auxiliary power input in the range of 20V and higher. VC_IN capacitance is also typically
1/10 of VC_OUT capacitance to avoid a significant voltage drop at VC_OUT when the VC switch is turned on.
Once V_{VC_OUT} falls below its UVLO threshold, the startup current source is turned back on, while the VC switch is
turned off, initiating a new PWM startup cycle. The UVLO_SEL input is used to select the VC_OUT UVLO
threshold between ~7 V and ~4 V, which should be slightly below the minimum falling UVLO threshold of the
PWM controller.
If VC_OUT is not used, VC_IN must be connected to the low voltage bias supply of the PWM controller to ensure
proper operation.
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