TMS320VC5441_17 Datasheet, PDF (21/91 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Introduction
Table 2−3. Signal Descriptions (Continued)
NAME
TYPE†
DESCRIPTION
A_INT¶#
B_INT¶#
C_INT¶#
D_INT¶#
A_NMI¶#
B_NMI¶#
C_NMI¶#
D_NMI¶#
A_RS#
B_RS#
C_RS#
D_RS#
RESET#
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
I
External user interrupts. A_INT−D_INT are prioritized and are maskable by the interrupt mask register (IMR) and the
interrupt mode bit. The status of these pins can be polled and reset by way of the interrupt flag register (IFR).
I
Nonmaskable interrupts. x_NMI is an external interrupt that cannot be masked by way of the INTM bit or the IMR. When
x_NMI is activated, the processor traps to the appropriate vector location.
Reset. x_RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the CPU
I
and peripherals. When x_RS is brought to a high level, execution begins at location 0FF80h of program memory. x_RS
affects various registers and status bits.
I
Global/HPI reset. This signal resets the four subsystems and the HPI.
SUPPLY PINS
VCCA
CVDD
DVDD
VSS
VSSA
Dedicated power supply that powers the PLL. VDD = 1.6 V
Dedicated power supply that powers the core CPUs. CVDD = 1.6 V
S
Dedicated power supply that powers the I/O pins. DVDD = 3.3 V
Digital ground. Dedicated ground plane for the device.
Analog ground. Dedicated ground for the PLL. VSSA can be connected to VSS if digital and analog grounds are not
separated.
TESTB||
TESTC||
TESTD||
No connection
EMULATION/TEST PINS
TCK¶#
Standard test clock. This is normally a free-running clock signal with a 50% duty cycle. Changes on the test access
I
port (TAP) input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test-data
register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK.
TDI¶
I
Test data input. Pin with an internal pullup device. TDI is clocked into the selected register (instruction or data) on a
rising edge of TCK.
TDO
O/Z§
Test data pin. The contents of the selected register is shifted out of TDO on the falling edge of TCK. TDO is in
high-impedance state except when the scanning of data is in progress.
TMS¶
Test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising
I
edge of TCK.
TRSTkh
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
I
operations of the device. If TRST is driven low, the device operates in its functional mode, and the IEEE
standard 1149.1 signals are ignored. Pin with internal pulldown device.
EMU0
I/O/Z
Emulator interrupt 0 pin. When TRST is driven low, EMU0 must be high for the activation of the EMU1/OFF condition.
When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as I/O.
† _{I = Input, O = Output, S = Supply, Z = High Impedance}
‡ _{This pin has an internal bus holder controlled by way of the BSCR register in TMS320C54x cLEAD core of DSP subsystem A.}
§ _{This pin is placed in high-impedance when the EMU1/OFF pin operates as OFF and when EMU1/OFF = 0, this case is exclusively for testing}
and emulation purposes.
¶ _{This pin has an internal pullup resistor.}
# _{These pins are Schmitt triggered inputs.}
|| _{This pin is used by Texas Instruments for device testing and should be left unconnected.}
kThis pin has an internal pulldown resistor.
hAlthough this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,
a buffer is recommended to ensure the VIL and VIH specifications are met.
NOTE: Pins highlighted in grey indicate the multiplexed function of the pin.
December 1999 − Revised October 2008
SPRS122F
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