THS3091DG4 Datasheet, PDF (21/36 Pages) Texas Instruments – HIGH-VOLTAGE, LOW-DISTORTION, CURRENT-FEEDBACK OPERATIONAL AMPLIFIERS

THS3091
THS3095
www.ti.com........................................................................................................................................ SLOS423G – SEPTEMBER 2003 – REVISED OCTOBER 2008
2500
2000
V_S = ±15 V and ±5 V
1500
1000
1.21 kΩ 1.21 kΩ
500
−
50 Ω ^VO
+
0
100 k
1M
10 M
100 M 1 G
f − Frequency − Hz
Figure 70. Power-Down Output Impedance vs
Frequency
As with most current feedback amplifiers, the internal
architecture places some limitations on the system
when in power-down mode. Most notably is the fact
that the amplifier actually turns ON if there is a ±0.7 V
or greater difference between the two input nodes
(V+ and V–) of the amplifier. If this difference
exceeds ±0.7 V, the output of the amplifier creates an
output voltage equal to approximately [(V+ – V–) –0.7
V] × Gain. This also implies that if a voltage is applied
to the output while in power-down mode, the V– node
voltage is equal to V_O(applied) × R_G/(R_F + R_G). For low
gain configurations and a large applied voltage at the
output, the amplifier may actually turn ON due to the
aforementioned behavior.
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
POWER-DOWN REFERENCE PIN
OPERATION
In addition to the power-down pin, the THS3095
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the PD pin. In most split-supply
applications, the reference pin is connected to
ground. In either case, the user needs to be aware of
voltage-level thresholds that apply to the power-down
pin. The tables below show examples and illustrate
the relationship between the reference voltage and
the power-down thresholds. In the table, the threshold
levels are derived by the following equations:
PD ≤ REF + 0.8 V for disable
PD ≥ REF + 2.0 V for enable
where the usable range at the REF pin is
V_S– ≤ V_REF ≤ (V_S+ – 4 V).
The recommended mode of operation is to tie the
REF pin to midrail, thus setting the enable/disable
thresholds to V_midrail + 2.0 V and V_midrail + 0.8 V
respectively.
POWER-DOWN THRESHOLD VOLTAGE LEVELS
SUPPLY REFERENCE PIN ENABLE DISABLE
VOLTAGE (V) VOLTAGE (V) LEVEL (V) LEVEL (V)
±15, ±5
0.0
2.0
0.8
±15
2.0
4.0
2.8
±15
–2.0
0.0
–1.2
±5
1.0
3.0
1.8
±5
–1.0
1.0
–0.2
+30
15
17
15.8
+10
5.0
7.0
5.8
Note that if the REF pin is left unterminated, it will
float to the positive rail and will fall outside of the
recommended operating range given above (V_S– ≤
VREF ≤ V_S+ – 4 V). As a result, it will no longer serve
as a reliable reference for the PD pin and the
enable/disable thresholds given above will no longer
apply. If the PD pin is also left unterminated, it will
also float to the positive rail and the device will be
enabled. If balanced, split supplies are used (±Vs)
and the REF and PD pins are grounded, the device
will be disabled.
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Achieving optimum performance with a
high-frequency amplifier, like the THS3091/5,
requires careful attention to board layout parasitic and
external component types.
Recommendations that optimize performance include:
• Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
• Minimize the distance [< 0.25 inch (6,35 mm)]
from the power supply pins to high-frequency
0.1-µF and 100-pF decoupling capacitors. At the
device pins, the ground and power plane layout
should not be in close proximity to the signal I/O
pins. Avoid narrow power and ground traces to
minimize inductance between the pins and the
decoupling capacitors. The power supply
connections should always be decoupled with
these capacitors. Larger (6.8 µF or more)
tantalum decoupling capacitors, effective at lower
frequency, should also be used on the main
supply pins. These may be placed somewhat
Copyright © 2003–2008, Texas Instruments Incorporated
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