LP87332B-Q1 Datasheet, PDF (21/73 Pages) Texas Instruments – Dual High-Current Buck Converter and Dual Linear Regulator

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Voltage
Voltage decrease because of load
LDOx_VSET[4:0]
Powergood
LP87332B-Q1
SNVSAT2 – JUNE 2017
Resistive pull-down
(if enabled)
Time
Enable
LDO_STAT(LDOx_STAT) 0 1
0
LDO_STAT(LDOx_PG_STAT) 0
1
01
0
INT_LDO(LDOx_PG_INT) 0
10
1 01 0
10
nINT
LDO_MASK(LDOx_PGF_MASK) = 0
LDO_MASK(LDOx_PGR_MASK) = 0
Powergood Host clears
interrupts interrupts
Figure 10. LDO Regulator Enable and Disable
The EN input pin have an integrated pulldown resistor. The pulldown resistor is controlled with EN_PD bit in
CONFIG register.
7.3.5.2 Changing Output Voltage
The output voltage of the regulator can be changed by writing to the BUCKx_VOUT / LDOx_VOUT register. The
voltage change for buck regulator is always slew-rate controlled, and the slew-rate is defined by the
BUCKx_SLEW_RATE[2:0] bits in BUCKx_CTRL_2 register. During voltage change the forced PWM mode is
used automatically. When the programmed output voltage is achieved, the mode becomes the one defined by
load current, and the BUCKx_FPWM bit in BUCKx_CTRL_1 register.
The voltage change and Power-Good interrupts are shown in Figure 11.
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